HIGH PERFORMANCE SCALABLE MIXED-RADIX-2n SERIAL-SERIAL MULTIPLIERS FOR GF(2m)
Abstract
In this paper, two new high performance bidirectional mixed radix-2n serial-serial multipliers for the finite field GF(2m) are presented. The input operands are serially entered one digit at a time for the first operand and two digits at a time for the second operand. The output result is computed serially one digit at a time. The reduction polynomial is also fed serially to the structure in the same manner so that changing the reduction polynomial will not require rewriting or rewiring the structure. The structures utilize a serial transfer which reduces the bus width needed to transfer data back and forth between memory and multiplication unit. The structures possess features of regularity, modularity and scalability which are a design requirement for an efficient utilization of FPGA resources. The new twin pipe design has improved the area-time performance by ~37% when compared with the best existing radix-2n serial-serial multipliers for the finite field GF(2m) . Furthermore, it is the first twin pipe bidirectional radix-2n serial-serial multiplier for the finite field GF(2m) reported in the literature. The twin pipe multiplier can be used to perform two successive K-digit multiplications in 2K + 6 cycles without truncating the results. As a consequence, a new data can be fed into the multiplier every K + 3 cycles. A radix-4 version of the proposed architecture has been designed, simulated and synthesized using Xilinx ISE 10.1 targeting a Xilinx Virtex-5 FPGA.
This paper was recommended by Regional Editor Krishna Shenai.
