Journal of Circuits, Systems and Computers

It is shown that a diminished-1 adder, with minor modifications, can be also used for the modulo 2ⁿ + 1 addition of two n-bit operands in the weighted representation, if the sum of its input operands is decreased by one. This modified diminished-1 adder can perform n-bit modulo 2ⁿ + 1 addition in less area and time than solutions that are based on the use of binary adders and/or weighted modulo 2ⁿ + 1 adders. Therefore, it can be applied effectively to all weighted modulo 2ⁿ + 1 arithmetic components that finally derive two n-bit addends. A small number of weighted arithmetic components have in the past adopted such a scheme without presenting this general theory. By applying this idea, we propose novel multi-operand modulo 2ⁿ + 1 adders (MOMAs) and residue generators (RGs). Experimental results indicate that the resulting arithmetic components offer significant savings in delay, implementation area and average power consumption compared to the currently most efficient solutions.

This paper describes the design and implementation of an RF CMOS quadrature LC voltage-controlled oscillator in a 0.35 μm technology. The proposed oscillator employs the switched tail transistor topology and differential switch capacitor tuning to achieve low phase noise operation. A modified series coupling mechanism is used for quadrature signal generation with wide output signal swing. The oscillator core circuit was designed to operate with a 2.5 V power supply voltage with a 4 mA total supply current. Measurement results showed that the prototype oscillator could achieve a nominal oscillation frequency of 2.2 GHz with -110 dBc/Hz phase noise at 1 MHz offset frequency.

The design and analysis of some new voltage controlled oscillators with sinewave output are proposed. The configurations are based on the implementation of double-integrator loop (DIL) using the Current Feedback Amplifier (CFA) device. For voltage control of the time constants of the DIL, the ICL-8013 multiplier element has been appropriately utilized in a feedforward/feedback connection within the loop. The oscillation frequency (ω_o) is tunable by the d.c. control voltage (V_c) of the multiplier. The active ω_o-sensitivity relative to the CFA port errors (ε) is quite low. The VCO practical performance had been tested both with hardware implementation and with PSPICE macromodel simulation, in a typical frequency range of 50 KHz–1.5 MHz.

Buffer insertion plays an important role in circuit performance and signal integrity especially in deep submicron technologies. The stage at which buffers are inserted in a design has a large impact on the design quality. Early buffer insertion may cause misestimation due to unknown cell locations whereas buffer insertion after placement may not be very effective because the cell locations have been fixed and buffer resources may be distributed inappropriately.

In this paper, a buffer planning algorithm for floor-placement design flow is presented. This algorithm creates a map of buffer requirements in various regions of the design at the floorplanning stage and then enforces the detailed placer to distribute white spaces with respect to the estimated buffer requirement map.

Experimental results show that the proposed method improves the performance of attempted circuits with fewer buffers. Furthermore, results show that congestion, routability and design convergence are improved and the auxiliary loops are avoided in the proposed design flow. Our analyses and experiments show that the CPU time overhead of this algorithm is very small.

While Maximum-Likelihood (ML) is the optimum decoding scheme for most communication scenarios, practical implementation difficulties limit its use, especially for Multiple Input Multiple Output (MIMO) systems with a large number of transmit or receive antennas. Tree-searching type decoder structures such as Sphere decoder and K-best decoder present an interesting trade-off between complexity and performance. Many algorithmic developments and VLSI implementations have been reported in literature with widely varying performance to area and power metrics. In this semi-tutorial paper we present a holistic view of different Sphere decoding techniques and K-best decoding techniques, identifying the key algorithmic and implementation trade-offs. We establish a consistent benchmark framework to investigate and compare the delay cost, power cost, and power-delay-product cost incurred by each method. Finally, using the framework, we propose and analyze a novel architecture and compare that to other published approaches. Our goal is to explicitly elucidate the overall advantages and disadvantages of each proposed algorithms in one coherent framework.

This paper presents two novel Floating Current Source (FCS)-based CMOS negative second generation current conveyor (CCII-) realizations suitable for very large scale implementation. The proposed realizations provide high voltage and current tracking accuracy, as well as large voltage and current transfer bandwidths. Simulation results show that the first proposed wide-band CCII- bandwidth is about 972 MHz. Targeting low-power dissipation, a second low-power version of the wide-band CCII- is proposed at the expense of lower bandwidth and accuracy. The proposed CCII- realizations are layout-friendly because they can be easily fabricated in a systematic modular layout fashion. In addition, a fair comparison is held between the proposed realizations and the only FCS-based CCII- realizations in the literature to show the strength of the proposed circuits. The proposed two CCII- realizations show excellent immunity to process variations and transistor mismatch. In addition, they are insensitive to the temperature variations. Finally, two common CCII- applications are presented.

In this paper, a Tow–Thomas biquadratic filter designed in square root domain is proposed. The presented filter is constructed with a lossy integrator, a lossless integrator, and a summer block. To the best knowledge of the authors, the filter is the first square root domain Tow–Thomas filter in the literature. The state space synthesis method is used to design the biquadratic filter. The filter operated at 2.5 V supply voltage is simulated by using SPICE simulation program with 0.25 μm TSMC CMOS model parameters. Simulation results are in good agreement with theoretical results that the cut-off frequency and quality factor of the filter are tunable electronically.

In this paper we present a technique to collapse a CMOS gate into an equivalent inverter. This technique considers deep submicron effects such as mobility degradation and velocity saturation as well as operation regions of both the NMOS and PMOS networks of the considered CMOS gate. In addition, the model accounts for the effect of the gate's internodal capacitances on the behavior of the equivalent Series Connected MOSFET Structure. Depending on the CMOS inverter transition time model presented in Ref. 1, the developed model has accurately predicted the transition time of different CMOS gates. Considering various loads, input switching, and transistor sizes, the model shows an average error of 6%, including the error introduced by the inverter model, as compared to BSIM3v3 using Spectre.

This paper proposes a methodology for supporting the design of fault-tolerant computers for real-time applications. To this end, the paper first presents steps of fault tolerance and describes mechanisms that can be used to realize them. Then, the design options consisting of described mechanisms are proposed and a table summarizing them is designed. From that, the paper proposes a flowchart for choosing between the many various design options available for building a redundant computer system. Choosing an optimal design option is performed according to the number of redundant computers, the mode of operation of redundant computers, the computer failure mode and the severity of the real-time constraint. Finally, graphical models for sequencing the mechanisms of design options are proposed. The main merit of the proposed methodology includes a spectrum of design options of fault-tolerant mechanisms for real-time computers tolerating a single fault at a time and a guide for choosing between them.

A number of sinusoidal oscillators using current differencing buffered amplifiers (CDBAs) have been reported in the literature. However, only three of them are canonic quadrature oscillators (i.e., requiring two capacitors). The aim of this letter is to present additional realizations of single/dual-resistance-controlled quadrature oscillators using CDBAs. Four voltage-mode quadrature oscillators are proposed, which provide the following advantageous features: (i) use of reduced and canonic component count, viz. two CDBAs, three/four resistors and two capacitors, (ii) all passive components are grounded or virtually grounded, which is favorable from integration point of view and (iii) independent and non-interactive resistor control of the condition of oscillation (CO) and the frequency of oscillation (FO). Simulation results verifying the workability of the proposed circuits have been included.

A novel adaptive current biased CLASS-A/shallow AB RF power amplifier is demonstrated in this paper. By theoretical deduction, a prototype is described to improve the linearity of a linear PA. With the realization on Jazz 0.35 μm SiGe HBT process and test verification, the novel adaptive current biased RF power amplifier shows 3 ~ 7 dB improvement of the ACPR at the output power of 19 dBm to meet the demand of CDMA IS95 spectrum mask without debasing the efficiency.

In this paper, two new high performance bidirectional mixed radix-2ⁿ serial-serial multipliers for the finite field GF(2^m) are presented. The input operands are serially entered one digit at a time for the first operand and two digits at a time for the second operand. The output result is computed serially one digit at a time. The reduction polynomial is also fed serially to the structure in the same manner so that changing the reduction polynomial will not require rewriting or rewiring the structure. The structures utilize a serial transfer which reduces the bus width needed to transfer data back and forth between memory and multiplication unit. The structures possess features of regularity, modularity and scalability which are a design requirement for an efficient utilization of FPGA resources. The new twin pipe design has improved the area-time performance by ~37% when compared with the best existing radix-2ⁿ serial-serial multipliers for the finite field GF(2^m) . Furthermore, it is the first twin pipe bidirectional radix-2ⁿ serial-serial multiplier for the finite field GF(2^m) reported in the literature. The twin pipe multiplier can be used to perform two successive K-digit multiplications in 2K + 6 cycles without truncating the results. As a consequence, a new data can be fed into the multiplier every K + 3 cycles. A radix-4 version of the proposed architecture has been designed, simulated and synthesized using Xilinx ISE 10.1 targeting a Xilinx Virtex-5 FPGA.

This paper presents a resource-shared 8-bit (RS8) architecture for the AES algorithm, which aims at compacting the hardware architecture and allows hardware resources to be shared efficiently between encryption and decryption without using a memory. The RS8 architecture only requires one combined S-box/S^-1-box for encryption, decryption and key expansion. The RS8 architecture implements the multiplicative inverse in the composite field GF((2⁴)²) with resource sharing methods. In addition, the number of XOR gates used by the proposed combined MixColumns/InvMixColumns module is less than half that of the conventional 32-bit architecture. When comparing the RS8 architecture with the conventional 32-bit architecture on a Xilinx Spartan2 FPGA, the number of total equivalent slices is reduced by 51%. Additionally, the highest operation frequency of the RS8 architecture is 66 MHz, and the throughput is 24 Mbps. Therefore, the performance of the RS8 architecture is sufficient for low-area applications such as wireless network devices and radio frequency identification (RFID).

In this paper, some electromagnetic interference (EMI) suppression techniques are studied and discussed for compact LED lamp drivers in residential lighting applications. A laboratory prototype with EMI suppression design is built and tested. Experimental results verify the feasibility of the studied schemes.