Journal of Circuits, Systems and Computers

Singular Value Decomposition (SVD) is one of the most useful techniques for analyzing data in linear algebra. SVD decomposes a rectangular real or complex matrix into two orthogonal matrices and one diagonal matrix. The proposed Quantum-SVD algorithm interpolates the non-uniform angles in the Fourier domain. The error of the Quantum-SVD approach is some orders lower than the error given by ordinary Quantum Fourier Transformation. Our Quantum-SVD algorithm is a fundamentally novel approach for the computation of the Quantum Fourier Transformation (QFT) of non-uniform states. The presented Quantum-SVD algorithm is based on the singular value decomposition mechanism, and the computation of Quantum Fourier Transformation of non-uniform angles of a quantum system. The Quantum-SVD approach provides advantages in terms of computational structure, being based on QFT and multiplications.

Low-noise amplifiers (LNAs) are critical to a wide variety of electronic circuits. In the design phase preceding fabrication, an LNA needs to be designed for a given set of specifications (e.g., gain, noise-figure, power consumption, etc.), which tend to be application-dependent. Typically, LNA design using commercial computer-aided design (CAD) tools can be human-intensive and requires a certain degree of expertise. This paper presents a systematic multi-phase CAD approach for the design of LNAs. In the first phase, a quick pre-analysis of the given LNA specifications is carried out leading to the selection of an appropriate LNA topology. In the second phase, an initial design of the LNA is generated employing an appropriate design procedure. Finally, the initial design is adjusted/fine-tuned so as to meet/exceed the given specifications, where necessary. The advantages of the proposed approach are shown through several practical LNA design examples in 0.18 μm CMOS technology.

A compact high-speed low-power rail-to-rail buffer amplifier, which is suitable for driving heavy capacitive loads, is proposed. The buffer amplifier is composed of a pair of push-pull output transistors with two feedback loops consisting of a pair of complementary error amplifiers and a pair of complementary common-source amplifiers. The buffer draws little current while static but has a large driving capability while transient. A mutual bias scheme is also proposed to reduce the power consumption and the die area for LCD applications. An experimental prototype buffer amplifier implemented in a 0.35 μm CMOS technology demonstrates that the settling time is 1.5 μs for a voltage swing of 0.1 ~ (VDD–0.1) V under a 600 pF capacitance load. Quiescent current of 4 μA is measured. The area of this buffer is 32 × 109 μm².

It has been found by the office of the Compliance & University RIO at the University of Central Florida (UCF) on behalf of Robert DeMara and Carthik Sharma that the concerned paper contains original text, tables, and figures from the sources authored or co-authored by the complainant. The respondent (Javad Sababeh) rebutted with two emails and stated that he had used the complainant's ideas and some text in the source papers. After carefully examining the materials provided by both sides, and considering the weight of evidence available and the request of the office of the Compliance & University RIO at the UCF, we retract this article.

In partially reconfigurable devices like FPGA, logic resources and communication channels can be reconfigured without affecting other section of the device. This allows parallel execution of multiple tasks on a FPGA. Due to limited resources on a FPGA, an effective management for efficient execution of tasks is required.

We present a new approach for management of FPGA logic resources and also communication channels in an online task placement. The approach creates communication channels between the tasks and also tasks with I/O elements without requiring extra computation overhead. We present a fast algorithm for searching MERs for management of FPGA space. Then, we present a exact routing algorithm to find distance and create exact path between two set of tasks. A new fitting strategy based on the rate of communication between the tasks is also presented. The results indicate the proposed strategy and also its combination with some other known strategies can improve the quality of placement.

Hardware interpretation is an attractive choice for implementing the Java virtual machine (JVM) in low-end embedded systems. However, the hardware interpretation of complex bytecodes is so expensive that most low-end embedded systems rely on slow software interpreters in processing complex bytecodes. This paper proposes a low-cost hardware approach for accelerating the interpretation of eight complex bytecodes: four object manipulation and four method invocation bytecodes. The proposed approach occupies 204 LUTs in a Xilinx FPGA and reduces by up to 61.5% the number of instructions executed in running the benchmarks considered in this paper.

This paper presents a single-stage high-frequency full-bridge electronic ballast for high-pressure mercury lamps in high-luminance LCD projector systems. The studied electronic ballast is found to have high conversion efficiency due to its single-stage circuit with zero-voltage switching features. A high power factor can be achieved by using developed single-stage topology. The operation principles and design considerations are analyzed and discussed in detail. A laboratory prototype is designed and implemented for driving a 150 W projector lamp. The simulation and experimental waveforms are given to verify the feasibility of the proposed method.

In this paper, we present a new method for characterization of radio frequency Power Amplifier (PA) in the presence of nonlinear distortions which affect the modulated signal in Radiocommunication transmission system. The proposed procedure uses a gray box model where PA dynamics are modeled with a MIMO continuous filter and the nonlinear characteristics are described as general polynomial functions, approximated by means of Taylor series. Using the baseband input and output data, model parameters are obtained by an iterative identification algorithm based on Output Error method. Initialization and excitation problems are resolved by an association of a new technique using initial values extraction with a multi-level binary sequence input exciting all PA dynamics. Finally, the proposed estimation method is tested and validated on experimental data.

Modern electronic products increasingly require high speed, high density, and low-voltage operation. In such designs, the power-delivery system could be affected by input noise to the point that it becomes unstable. Simultaneous switching noise (SSN) is a major factor that interferes with power integrity. Although decoupling capacitors cannot effectively alleviate the problem of SSN, they have been generally used in the HP Simulation Program with Integrated Circuit Emphasis model for reducing SSN. The differential I/O buffer information specification (D-IBIS) model uses equivalent circuits to describe the behavior of an integrated circuit. In this study, we propose a novel method for effectively reducing SSN evaluated by an enhanced D-IBIS model with decoupling capacitors and a high-frequency low-impendence circuit. We show that this new method reduces noise by about 40–64% compared to traditional design methodologies.

In this paper, a cross-coupled complementary inductance–capacitance voltage controlled oscillator (LCVCO) with low phase noise and wide tuning range is presented. It has a multi-band topology and was fabricated with RF CMOS technology. For the purpose of lowering the K_VCO and reducing the nonlinearities of varactors, the sizes of the varactors are set small. Also noise filtering technique is adopted to minimize up-conversion of the low frequency noise as well as down-conversion of the high frequency noise, thus the phase noise performance of the VCO is greatly improved. Simulation and experimental results indicate that the LCVCO displays a phase noise of -126.1 dBc at 900 kHz offset in worst case with a tuning range from 1.76 to 1.96 GHz.

The choice of the best color system representation is an efficient technique in background modeling and a fundamental task in detecting foreground objects on both static and dynamic scenes. In this paper, we present some algorithms consecrated for images color segmentation's issued from a soccer video. This manuscript is prominent for many next computers vision studies. Indeed, in this paper many segmentation techniques using pixel values are developed (statistical, fuzzy tools) and gives a high robustness level even in presence of significant shadows and highlights. The use of RGB color space to represent a pixel is not obvious to lead to valuable results in certain situations, for this reason, we proposed a new approach using color to improve players detection in images by determining the three significant color components on the one hand, and using statistical theory to model the background on the other hand. In fact the use of color is widely employed by many researchers. Also this paper presents experimental results of soccer scenes, which will evaluate the proposed methods in order to extract players and eliminate the effects of shadows, and to keep the best levels.

In this paper, we present a fast and simple SPICE-based technique for the performance characterization of BJT mixers. First, exploiting fundamental concepts, an AC equivalent circuit of a radio-frequency bipolar junction transistor mixer is derived. Second, this equivalent circuit is used to estimate the conversion gain, noise-figure, and nonlinearity characteristics of the mixer. The proposed technique has been validated using simulations on integrated and discrete transistor based mixer circuits.

In this paper, three dual-mode (mixed-mode) analog filters using only grounded capacitors and two to three second-generation current conveyors (CCIIs) are presented. The first proposed filter can provide a transimpedance-mode (TIM) second-order filter transfer function (TF), and is free from passive component matching constraints, which is advantageous in integrated circuit (IC) design. Other two mixed-mode filters having the property of tunability are derived from the first proposed filter. However, the developed filters in this work, like other active filters, suffer from nonidealities such as nonideal gain and parasitic impedance effects which increase the order of the filter TFs; accordingly, stability problem may arise. In this study, stability analysis using gain and phase margins is accomplished. To explain the claimed ideas, several computer simulations and an experimental test are performed.

A compact power-on-reset pulse generator (POR-PG) circuit with a low-power and low-voltage operation capability is presented. Proposed POR-PG was fabricated in 0.5 μm 2P3M CMOS process. It was determined from simulations and measurements that proposed POR-PG works supply voltage levels between 1.8 V and 3.3 V and supply voltage rise times between 100 ns and 1 ms. POR-PG has very small silicon footprint. Layout size of proposed POR-PG circuit was 120 μm × 5 μm in 0.5 μm CMOS process. Comparing with other POR-PG circuits in the literature, proposed design enjoys lowest power consumption (< 6 μW), smallest silicon footprint, widest supply voltage range, and additional features such as brown-out detection capability. These achieved by using a unique cascadable POR delay element that consumes very low-power.