Journal of Circuits, Systems and Computers

This paper presents two novel active-feedback single Miller capacitor frequency compensation techniques for low-power three-stage amplifiers. These techniques include the active-feedback single Miller capacitor frequency compensation (AFSMC) and the dual active-feedback single Miller capacitor frequency compensation (DAFSMC). In the proposed techniques, only one Miller capacitor in series with a current buffer is utilized. The main advantages of the proposed three-stage amplifiers are the enhanced unity-gain bandwidth and the reduced silicon area. Small-signal analyses are performed and the design equations are obtained. Extensive HSPICE simulation results are provided to show the usefulness of the proposed AFSMC and DAFSMC amplifiers in both large and small capacitive loads.

Data hiding in the LSB of audio signals is an appealing steganographic method. This is due to the large volume of real-time production and transmission of audio data which makes it difficult to store and analyze these signals. Hence, steganalysis of audio signals requires online operations. Most of the existing steganalysis methods work on stored media files. In this paper, we present a steganalysis technique that can detect the existence of embedded data in the least significant bits of natural audio samples. The algorithm is designed to be simple, accurate, and to be hardware implementable. Hence, hardware implementation is presented for the proposed algorithm. The proposed hardware analyzes the histogram of an incoming stream of audio signals by using a sliding window strategy without needing the storage of the signals. The algorithm is mathematically modeled to show its capability to accurately predict the amount of embedding in an incoming stream of audio signals. Audio files with different amounts of embedded data were used to test the algorithm and its hardware implementation. The experimental results prove the functionality and high accuracy of the proposed method.

Homogeneous Boolean functions have many applications in computing systems, e.g., cryptography. This paper presents a factorization algorithm for reducing the quantum cost of the reversible circuits for that class of Boolean functions. The algorithm reduces the multi-calculation of any common parts of the circuit. This allows Homogeneous Boolean related applications to be implemented efficiently on novel computing paradigms such as quantum computers and low power devices.

Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, memory access conflicts caused by multiple memory buses limit the overall performance. We propose and evaluate the configurable memory address shuffler integrated in memory access arbiter for the parallel memory system in a soft processor. The novel address shuffling algorithm profiles memory access pattern of the application, produces the access conflict graph, relocates decomposed memory sub-pages based on the access conflict graph, and finally generates a synthesizable code of the address shuffler. The address shuffler efficiently translates the requested memory addresses into the shuffled addresses such that the amount of simultaneous accesses to the identical physical memory block diminishes. The reconfigurability of the address shuffler enables the adaptive address shuffling depending on the memory access pattern of an application running on the soft processor. The configurable address shuffler removes 80% of access conflicts on average for benchmarks where the hardware overhead of the shuffler is 1592 LUTs which is 14% of LUT size of the processor core.

A reduced supply voltage must be accompanied by a reduced threshold voltage, which makes this approach to power saving susceptible to process variation in transistor parameters, as well as resulting in increased subthreshold leakage. While adaptive body biasing is efficient for both compensating process variation and suppressing leakage current, it suffers from a large overhead of control circuit. Most body biasing circuits target an entire chip, which causes excessive leakage of some blocks and misses the chance of fine grain control. We propose a new adaptive body biasing scheme, based on a lookup table for independent control of multiple functional blocks on a chip, which controls leakage and also compensates for process variation at the block level. An adaptive body bias is applied to blocks in active mode and a large reverse body bias is applied to blocks in standby mode. This is achieved by a central body bias controller, which has a low overhead in terms of area, delay, and power consumption. The problem of optimizing the required set of bias voltages is formulated and solved. A design methodology for semicustom design using standard-cell elements is developed and verified with benchmark circuits.

This paper surveys the state-of-the-art parallel techniques for multiprocessor architectures, and studies its implication for Java programs, which are typically compiled at run-time. First, this paper overviews basic techniques of program parallelization in traditional static compilers, followed by a survey of successful parallelizing compilers. Then this paper introduces the latest research topics in this area, particularly focusing on the efforts of combining parallelizing techniques with Java virtual machines, including parallel compilation and parallel real-time garbage collection. Finally, this paper summaries the opportunities and challenges of parallelizing Java computing on multicore platforms.

Leakage power is becoming a key design challenge in current and future CMOS designs. Due to technology scaling, the leakage power is rising so quickly that it largely elevates the die temperature. In this paper, we deeply investigate the impact of leakage power on thermal profile in both 2D and 3D floorplanning. Our results show that chip temperature can increase by about 11°C in 2D design and 68°C for 3D case with leakage power considered. Then we propose a thermal-driven floorplanning flow integrated with an iterative leakage-aware thermal analysis process to optimize chip temperature and save leakage power consumption. Experimental results show that for 2D design, the max chip temperature can be reduced by about 8°C and the proportion of leakage power to total power can be reduced from 19.17% to 11.12%. The corresponding results for 3D are 60°C temperature reduction and 16.3% less leakage power proportion.

In this paper, we present a novel methodology for vector generation that maximizes the metric of datapath coverage for a given combinational logic circuit. The proposed methodology is based on Mixed Integer Linear Programming (MILP). The search of input vectors based on the datapath coverage metric is a satisfiability (SAT) problem. In order to obtain maximum coverage vectors, we use a novel model for the Boolean logic gates to translate the original SAT problem into an MILP optimization problem. Next, the new problem is solved following the MILP optimization environment and an exhaustive search strategy. We compare our proposed methodology with the exhaustive search algorithm. Experimental results and performance comparisons based on the large set of MCNC'91 suite of benchmark circuits are presented. They show significant speedups of MILP methodology against the exhaustive search algorithm for the complex circuits.

Predicate logic gates, components and a processor are proposed for space–time signals and computing. Voltage impulses are transmitted along two wires and the signals are considered as predicate expressions. The developed simple gates and components perform the predicate logical operations AND, NOT, and OR with these expressions. For design and verification of all components and the processor, the CPLD and FPGA boards and corresponding software are used. The designed processor is compatible with classical computers and applicable in the area of artificial intelligence as well as linguistic calculations, database machines, SQL servers, etc.

Multithreaded programming has become the dominant paradigm in computer architecture, mainly in the form of multi-core processors. The performance bottleneck of a multithreaded program is its critical path, whose length is its total execution time. As the number of cores within a processor increases, Network-on-Chip (NoC) has been proposed as a promising approach for inter-core communication. In order to optimize the performance of a multithreaded program running on an NoC based multi-core platform, we design and implement the critical-path driven router, which prioritizes inter-thread communication on the critical path when routing packets. The experimental results show that the critical-path driven router improves the execution time of the test case by 14.8% compared to the ordinary router.

This paper deals with the use of a minimal model for performing secure computations. The communication is based on a protocol which makes use of disjoint function decomposition and more precisely of minimal ESCT (Exclusive-or Sum of Complex Terms) expressions in order to perform a secure computation. The complexity of this protocol is directly proportional to the size of the ESCT expression in use, which is much smaller in comparison to other proposed minimal models (e.g., ESOP). Moreover, quantum algorithms are discussed that provide significant speedup to the process of producing the ESCT expressions, when compared to conventional ones. Hence, this paper provides a very useful application of the ESCT expressions in the field of cryptographic protocols.

A SAR (Synthetic Aperture Radar) antenna typically consists of a large planar array to obtain a directive pattern with low side lobe level. A multibeam SAR system requires a set of secondary beams, implementing some additional features. To protect the SAR operation from possible jammers ECCM (Electronic Counter-Countermeasure) capabilities can be implemented requiring an auxiliary beam which cover the portion of main pattern to be protected. A possible architecture of this secondary antenna system is here presented by using a set of radiating elements combined together to obtain the ECCM channel. To minimize the feeding network complexity and to maximize the system reliability, the ECCM antenna is a cluster of circular corrugated horns, eventually realized as a single-block unit.

To improve the shortcomings of long arbitration–allocation time and large power consumption in conventional network on chips, this paper proposes a high speed multi-resource arbiter with active virtual channel allocation. Through arbitrating the acknowledgement signals of virtual channels, the virtual channels can attend the arbitration–allocation process actively. Thus reduces the virtual channel allocation time. Furthermore, the proposed multi-resource arbiter has integrated the function of virtual channel allocation, which improves the performance and simplifies the design process simultaneously. Null convention logic units are used to make the circuit quasi-delay insensitive and high robustness. The proposed multi-resource arbiter is implemented based on SMIC 0.18 μm standard CMOS technology. Results have shown that the arbitration–allocation time of the arbiter is only 824.1 ps, which reduced 25.1% compared with the conventional one. The power consumption and the area are slightly larger than the conventional ones. The proposed high speed multi-resource arbiter is suitable for high performance and high robustness interconnections of on chip networks.

A new single input and five outputs high input impedance voltage-mode universal biquadratic filter using three DVCCs, five passive components is presented. The proposed circuit offers the following features: high input impedance, realization of all the standard filter functions, that is, high-pass, band-pass, low-pass, band reject and all-pass filters simultaneously, the use of grounded capacitor, orthogonal control of ω₀ and Q, no need to employ inverting type input signals, and no need to impose component choice except realizing the all-pass filter signal. A new quadrature oscillator circuit is also realized. PSPICE simulations using 0.35 μm TSMC CMOS parameters confirm the validity of the proposed circuit.

This paper presents a novel non-coherent receiving algorithm termed trigger receiving algorithm. In comparison with conventional coherent receiving method, the trigger receiving algorithm needs neither local template nor correlation operation, thus both circuit complexity and power consumption are drastically reduced. Based on the proposed algorithm, a fully integrated transceiver was implemented in a 0.18 μ m CMOS process. It occupies an area of 0.44 mm² and achieves a maximum chip rate of 40 Mbps with 7 mW energy consumption provided by a 1.8 V power supply.

An A/D converter based random bit generator which exploits continuous-time chaos is presented. The chaotic circuit, which is used as the core of the random bit generator generates double-scroll attractor the frequency spectrum of which spans up to 80 MHz. The chaotic circuit was fabricated using a 0.35 μm CMOS process and the chip area, excluding pads, is 0.06 mm². Power consumption of the integrated chip is 8 mW. Binary data obtained from the presented random bit generator pass the full NIST-800-22 test suite.