Journal of Circuits, Systems and Computers

Due to rapid growth in the integrated circuit (IC) industry, the demand for compact digital system design is high. However, the continued technology reductions made the feasibility of further scaling down transistor size more challenging. In response to the growing demand for ultra-compact IC designs, the revolutionary quantum-dot cellular automata (QCA) technology has emerged as a promising solution. In a digital era, the counters are widely adopted in the peer-to-peer process flow to establish a mechanism for generating unique values for each identifier/number. In this work, a unique synchronous and asynchronous counters architecture is proposed with a reliable D and T flip-flop design. The proposed QCA architecture is implemented and validated with the QCA designer tool. Furthermore, in QCA technology, unreliable QCA designs can lead to frequent errors and malfunctions in the implemented logic. To overcome this challenge, the proposed design prioritizes cell placement (the relative positions of QCA cells) to make the circuit more robust. As a result, the circuit can still produce the expected functionality even if some QCA cells malfunction. Hence, to ensure the reliability of the proposed QCA architecture, the missing cell defect analysis is carried out in comparison with existing state-of-the-art designs. Based on comparison results, the unique designs like the proposed multiplexer, D flip-flop and T flip-flop design exhibit success rates of 67.28, 77.04 and 85.15%, respectively. The experimental results demonstrate that the proposed counter-architecture outperforms existing architectures.

This paper presents a novel hardware architecture for Frequency Response Masking (FRM) Filter Bank based on Residue Number System (RNS) arithmetic for Digital Hearing Aids (DHA). FRM is a computationally efficient approach for filter bank design that separates different frequencies based on the Audiograms of a patient. However, filter banks are critical power-hungry elements that require high computational resources. Therefore, the proposed architecture aims to provide an efficient implementation of FRM filter banks, which can improve the value and affordability of DHAs. The proposed architecture employs FIR filters in direct form, linear phase, and poly phase using RNS arithmetic. This approach enables the performance of arithmetic operations in parallel and independently. The concepts are further extended for the efficient implementation of FRM filter bank. The results of the proposed architecture show that direct implementation reduces the delay when the number of taps increases in the FIR filter. However, to reduce computational resources and optimize the area requirement, a Folded RNS architecture is also proposed. The Folded RNS architecture offers hardware savings of 23–27% for a 40-tap FIR filter and 29–31% for a 60-tap FIR filter. Additionally, it improves speed by 13–15% for a 40-tap FIR filter and 16–19% for a 60-tap folded RNS FIR filter. The implementation of FRM filter bank using the folded FIR filter shows the same trend in hardware saving and speed improvement as in the case of FIR filters. These results demonstrate that the proposed hardware architecture has the potential to improve the efficiency and affordability of DHAs while enhancing the listening comfort, which can enhance the quality of life for patients with hearing impairments.

Point multiplication is the most expensive operation in ECC as it repetitively utilizes field multiplication. In this research, we propose an efficient FPGA-based point multiplication over Edwards25519. The majority of the enhancements stem from the invention of a novel field multiplier and the implementation of three general rules to achieve optimal scheduling of operations in the point multiplication. First, field multiplications with the longest path are given the highest precedence. Second, field multiplications with a greater number of output edges are given higher precedence. Third, priority is given to the field multiplications that compute the final outputs. The innovative field multiplier is based on the Karatsuba–Ofman multiplication method, which involves four steps. This multiplier uses fewer additions and subtractions than the original numbers. Additionally, it features a semi-systolic architecture with a few register layers, resulting in low CPD and latency. Compared to the most efficient previous work, the proposed point multiplication is 139% more efficient and 7% faster.

Due to the increasing number of applications for various purposes, including commercial, scientific, environmental, and military ones, Underwater Wireless Sensor Networks (UWSNs) have recently attracted substantial attention from academia and enterprises in research and development. Monitoring pollutants, tactical surveillance, tsunami alerts, and offshore drilling are some important applications. Due to acoustic transmission disruptions brought on by extreme noise, extraordinarily lengthy propagation delays, a high bit error rate, a constrained bandwidth, and interference, efficient sensor communication in UWSNs is a difficult challenge. Therefore, designing efficient communication among sensors and sinks is one of the fundamental research themes in UWSNs. This paper proposes an energy-efficient optimal cluster head (CH)-based routing in UWSNs. The proposed methodology consists of three stages namely, cluster formation, CH selection, and priority-based routing. In this study, initially, the clusters are formed using a k-means clustering algorithm. Then, the CHs are selected using the Adaptive Honey Badger optimization (AHBO) algorithm, which is used to reduce energy consumption and delay. AHBO is a combination of a honey badger, Levy flight, and genetic algorithm operators. After the CH selection process, data packets are transferred toward the base station through autonomous underwater vehicles (AUVs). The efficiency of the proposed approach is analyzed based on different metrics and performance compared with the different methods.

To minimize circuit design, a novel current-mode wave active filter (WAF) employing the extra-X current-controlled current conveyor transconductance amplifier (EX-CCCCTA) active building block (ABB), is presented in this paper. Unlike other WAFs in the research, this design uses a single EX-CCCCTA, and grounded passive components suitable for monolithic integration, and an electronic tuning capability to offer an appropriate response at high frequencies up to 10MHz approximately. Compared to their passive equivalents, active filters have tunable gain, monolithic integration compatibility, and appropriate input–output impedance. Furthermore, Monte Carlo analysis, total harmonic distortion (%THD), and noise analysis are used to validate the filter performances. The SPICE simulations verify the functional effectiveness of the proposed WAF.

Modular Multiplication (MM) plays a crucial role in public key cryptography and random numbers generation. Montgomery Modular Multiplication (MMM) Algorithm is the most popular method used for performing this operation. Currently, there are various Field Programmable Gate Array (FPGA)-based optimizations targeting the MMM implementation. However, many of these works suffer from complex critical path where multiplications and carry propagate additions are calculated at each clock cycle. This leads to a low computation throughput and limited frequency. This paper presents an efficient FPGA implementation of the MMM algorithm using compressors-4:2 (Comp-4:2s). Our objective is to realize a Hardware (HW) architecture which presents a best trade-off between computation throughput and occupied area. The execution performances of the MMM depend on both parameters: the radix-r and the modulus size. In fact, when the radix increases, the algorithm requires multiplications of form digits$\times$operands. On the other hand, when a long modulus is used, the HW implementation of the MMM needs long carry propagation paths. In this work we propose an approach to circumvent the required multiplications by decomposing the digits into coefficients powers of 2. Then, the multiplications are carried out by simple shifts and additions. The Carry Save Adders (CSAs) are employed to avoid the use of long carry chains. However, the combination of CSAs and the used radixes requires four-input adders. Our implementation is based on using the Comp-4:2s for the realization of regular CSAs structures. The challenge consists in the development of an optimized Comp-4:2 which must be completely integrated in single FPGA Slice. Our implementation solution allows the achievement of high computation throughput. The obtained critical path delay is independent of the operand size. The implementation on Virtex-7 circuit using a modulus of 1024-bit size shows that the MMM run in 1.31 and requires 2342 Slices.

In this work, we present a comprehensive study of the commutativity of fractional-order linear time-varying systems (LTVSs). Commutativity is a fundamental property in the analysis and control of dynamic systems and is often used to simplify the design of controllers. Fractional-order systems, which are characterized by a noninteger-order derivative, have been widely studied in recent years due to their ability to model a wide range of phenomena. However, the commutativity of fractional-order LTVSs has not been widely explored. In this work, we present a comprehensive study of the commutativity of fractional-order LTVSs. We first provide a mathematical definition of commutativity for these systems and demonstrate that it is equivalent to the commutativity of their transfer functions. We then propose a method for verifying the general condition for commutativity of fractional-order LTVSs under zero initial conditions (ICs) and prove it mathematically. Based on our findings, we realized that the commutative requirements, properties, theories, and conditions are general for fractional-order LTVSs, please observed that some fractional-order LTVSs are commutative, some are not commutative, while some are commutative under certain conditions. Based on this fact, we can say that not all fractional-order LTVSs are commutative.

We apply explicit commutative results to several examples of fractional-order LTVSs. Our theoretical and simulation results show a good agreement and prove that our fractional-order LTVSs are commutative under certain conditions, moreover, the commutativity property holds for certain conditions and classes of fractional-order LTVSs, but not for others. Because of the application of fraction commutativity in various fields of science and engineering, we find it necessary to come up with explicit results for the first time.

In many integrated circuit applications, where large passive resistors are prohibited, a tunable active resistor is necessary. This paper presents a compact and wide-range voltage-controlled grounded resistor that employs MOS transistors only. The design’s foundation is an active adjustable resistor that controls the NMOS transistor’s mode of operation. The proposed design is implemented using 0.18$\mu$m TSMC CMOS technology and is validated through post-layout simulations conducted in the Cadence Virtuoso environment. Furthermore, a tunable high-pass filter utilizing the proposed active resistor is also shown. The circuit is powered by 1.5V DC. According to the simulation findings, the resistance varies between 33k $\mathrm{\Omega }$ and 36G $\mathrm{\Omega }$, for an input voltage range $-$0.7–0.6v.

In this work, a transmission gate-based low-power ten FinFET (TGLP10T) single-ended read/write SRAM cell is proposed. The proposed cell achieves low leakage operation along with improved write-ability. The performance metric results obtained from TGLP10T are compared with five previously published bit-cell designs, i.e., conventional 6T (Con6T), robust transmission gate-based 10T SRAM (RTG10T), transmission gate-based variation resistant 9T SRAM (TGVR9T), PNN (PMOS-NMOS-NMOS) inverter-based 10T (PNN10T) and PPN (PMOS-PMOS-NMOS) inverter-based read decoupled 10T (PPNRD10T. The leakage power in proposed design is reduced by $1.27\times ∕1.15\times ∕1.33\times ∕1.15\times ∕1.00\times$ compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The write power and WSNM are improved by $1.07\times ∕1.40\times ∕0.87\times ∕1.63\times ∕0.78\times$ and $1.57\times ∕1.69\times ∕1.08\times ∕1.59\times ∕1.50\times ∕1.00\times$, respectively, compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The read delay and write delay are improved by $1.00\times ∕1.54\times ∕1.36\times ∕1\times ∕2.83\times$ and 1.68 $\times ∕2.35\times ∕1.82\times ∕2.89\times ∕1.77\times$, respectively, compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The proposed design shows the least data retention voltage compared to other SRAM bit-cells.

Named entity recognition is a crucial task in natural language processing, serving downstream tasks such as information extraction and question-answering systems. With the success of Transformer in the field of natural language processing, named entity recognition has made significant strides. However, despite these advancements, the recognition capability in specialized domains remains challenging. The distribution network system contains a vast amount of equipment maintenance text, characterized by inherent complexity and specialization, lacking effective recognition and extraction methods. To address this issue, we propose a vocabulary-enhanced named entity recognition method. Unlike the original named entity recognition methods, we employ a vocabulary adapter to enhance the understanding of text semantic information by integrating matching information between the dictionary and the text. This method strengthens the ability to extract specialized nouns. In conjunction with the TaCL-BERT pre-trained model, we conducted training on our self-constructed distribution network maintenance dataset, GNP-M, to better align the model with the context and specific entities of the electrical grid maintenance domain. Simultaneously, we compared our method with four other named entity recognition models, revealing satisfactory performance results.

With the rapid development of the Internet and network technology, network security has become increasingly prominent. Regarding the important issue of network attack detection, traditional methods often find it difficult to effectively capture and identify new types of network attack behaviors, while models based on deep learning and evolutionary algorithms are considered to better adapt to complex and ever-changing network attack environments. This paper aims to explore how to combine convolutional autoencoder (CAE) and genetic algorithm (GA) to construct an efficient network attack detection model and improve the ability of network security defense. First, the convolutional autoencoder is used to effectively learn the feature representation of network data, and combined with hierarchical attention mechanism, appropriate weights are assigned to classification tasks under different features and feature fusion is performed. Using GA to adaptively optimize random forest and improve its performance and robustness in network attack detection. Ultimately, achieving better network security protection results and effectively preventing and combating various network security threats. And conduct experimental verification on multiple datasets and compare with other benchmark methods. The results show that the model has achieved significant improvement in the detection of text network attacks, and can more effectively classify various types of attacks, bringing new technological breakthroughs and application prospects for network attack detection. It will also provide new ideas and methods for the further development of network security, effectively ensuring the safe and stable operation of network systems.

Mobile target tracking remains a significant issue in smart cities. Due to complex changes in time and space of targets, real-time tracking remains a challenging problem. As a result, this paper proposes a real-time tracking approach for moving objects by combining the advantages of YOLOv7 and SORT algorithms. First, we use the YOLOv7 algorithm for object detection, which has the characteristics of high accuracy and efficiency. Then, we apply the SORT algorithm to the target tracking stage, which estimates and updates the target state through Kalman filtering. The collaborative function of the two parts is expected to achieve high-quality tracking of moving targets. Besides, this paper also demonstrates experiments and analysis on image datasets. The experimental results show that the proposed algorithm has achieved good performance in real-time tracking of moving targets. Compared with traditional methods, it can more accurately predict the position and trajectory of targets and has better real-time performance. In addition, the proposed algorithm is equally effective for target tracking in complex scenes, such as multi-target tracking and target occlusion. Future research can further optimize the performance of algorithms to cope with more complex scenarios and problems.

As a critical financing method, supply chain finance (SCF) plays a vital role in addressing the financing challenges faced by small- and medium-sized enterprises (SMEs) and in promoting collaborative development within supply chains. However, SCF systems inevitably encounter complex risks of default contagion. Effectively detecting and assessing these risks, along with formulating reasonable financing strategies, are issues of common concern to both the academic and business communities. This study utilizes complex network theory to investigate the guaranteed warehouse financing model in supply chain finance. First, a complex network model of supply chain finance is constructed to analyze the transmission mechanisms of default contagion risk. This model effectively measures the ways and mechanisms of risk propagation. Second, a default probability model is developed to assess the risk magnitude for enterprises following default contagion. This model facilitates risk assessment and control, providing a scientific basis for financing decisions. Third, by constructing an SCF financing model, this study examines the financing decision-making behaviors of banks, manufacturers and retailers under various conditions. It reveals the interactions and interest trade-offs among participants in the guaranteed warehouse financing model. Finally, through simulation analysis, the study investigates the impact of different parameters on supply chain finance strategies. The results offer quantitative guidance for banks in setting loan quotas and provide a theoretical foundation for enterprises to formulate reasonable financing strategies in the guaranteed warehouse financing model.

Emergency communication is a key link to ensure the stable operation of communication networks. And large-scale multiple-input multiple-output (MIMO) technology can significantly improve coverage of communication systems. This work aims to optimize the backhaul process through deep neural network to improve the response speed and data transmission efficiency of base stations. Specifically, the proposed method uses deep neural network to represent the backhaul process of base stations, and explores data transmission under high efficiency and low delay. Simulation experiments are designed to verify performance advantages of the proposed method in large-scale MIMO wireless ad hoc networking scenarios, by using three comparison metrics. The experimental results show that the proposed method has a significant performance improvement in data transmission rate, system stability and resource utilization compared with traditional methods. Besides, the feasibility and effectiveness of the algorithm in practical application are verified by simulation and actual environment test. To sum up, the proposed algorithm can provide a new direction for the technical research in the field of emergency communication.

Wireless on-chip networks suffer from serious congestion problems due to the expansion of their network size and the joining of wireless nodes, and token passing is very inefficient in the case of low network injection. Aiming at the congestion problem and the inefficiency of token passing in wireless on-chip networks, this paper designs a three-hop congestion-aware routing mechanism in WiNoC. In the scheme of this paper, first, the congestion information is written into Head Flit for propagation through the information piggybacking method, in which the information piggybacking method does not introduce congestion information propagation overhead, second, the port with the smallest congestion value is selected for transmission through the three-hop congestion-aware routing algorithm to reduce the congestion within the subnetwork, and then the wireless node congestion is mitigated through the new wired and wireless packet division method, and finally, the power of wireless nodes is reduced through the dynamic MAC mechanism to reduce the power consumption of wireless nodes. The experimental results show that this paper’s scheme can reduce the intra-subnet congestion, balance the inter-subnet load, reduce the power consumption of wireless nodes, and reduce the latency by 44.6% compared with the basic wireless on-chip network using adaptive routing algorithm, and reduce the latency by 21.8% compared with the wireless on-chip network using global congestion-aware routing algorithm; in different traffic patterns, this paper achieves the highest saturation throughput in different traffic patterns, and the additional hardware overhead of the router increases by only 0.04%.

Recently, Internet of Things (IoT) technology has become popular and applicable in different fields. The exchangeable data through IoT systems are extremely huge. This poses a great challenge in constructing a scalable and reliable computing scheme for IoT environments. Therefore, an efficient computing scheme for an IoT-enabled healthcare environment was proposed in this paper. The computing scheme idea was based on the use of cloud, fog, mist and edge computing strategies after dividing their resources into N-tiers. For easy management, these tiers were clustered depending on their geographical distribution. The number of tiers for each computing strategy dynamically changed depending on the computing load. Each tier had its own capabilities. Therefore, selecting a computing strategy and its tier was achieved regarding the data requirements and the specs of each computing resource. To evaluate the proposed computing scheme, a network simulator package (NS-3) was used to construct a simulation for the IoT-enabled healthcare environment and the computing scheme. Most simulation results of our computing scheme were compared with the cloud/fog/mist, cloud/fog and cloud computing schemes. Finally, the simulation results proved that the proposed computing scheme outperformed the performance of other traditional computing schemes regarding the following performance metrics: Delay, utilization, energy consumption, beneficial users and different healthcare organization complexities.

EEG-based brain–computer interface systems have demonstrated impressive capability in the context of the broad use of deep learning. However, serious security flaws have been shown by their vulnerability to adversarial sample attacks. It is not possible to directly apply traditional attack strategies from the image domain to EEG signals because of their unique visualization and dynamic features. A unique multi-target smooth universal adversarial perturbation (MS-UAP) approach designed specifically for EEG data is presented in this paper to address this difficulty. We define a loss function and optimize parameters based on UAP for both target and nontarget class samples, respectively, to address the temporal nature of the EEG signal and the attack’s flexibility. Additionally, this research generates a smoothed adversarial sample by convolution operations, yielding a more disorienting effect, to avoid the introduction of physiologically untrustworthy square wave distortions caused by typical visual attack approaches. Three public EEG datasets were used for extensive testing and assessments, and the results show that MS-UAP successfully targets convolutional neural network (CNN) classifiers and launches simultaneous attacks on several classes, exhibiting strong model transferability. To ensure accurate attacks that go undetected, MS-UAP creates a single disturbance that is targeted at target classes and has the least negative effect on other classes. In order to facilitate effective real-time attacks, MS-UAP, an offline-generated universal perturbation template, can be smoothly incorporated into EEG data. The study is significant since it emphasizes how important it is to improve BCI system security and promote the creation of stronger defenses.

To enhance the power-to-hydrogen (P2H) efficiency and multiple energy utilization efficiency of the hydrogen-electric integrated energy system (HE-IES), an optimal operation framework considering the P2H factor is proposed. First, the proton exchange membrane electrolytic cells model which considers mass transfer characteristics is established. Efficient hydrogen production operating parameters are obtained through simulation to maximize the P2H efficiency. Second, the HE-IES is established, including the hydrogen flow system, wind power (WP), energy storage systems, gas boiler, combined heat and power and methanation unit. Based on the characteristics of the devices and efficient hydrogen operating parameters, the optimal operation framework considering the P2H efficiency factor is proposed. To realize the low economic operating costs and maximize the utilization of WP, a multi-objective function based on fuzzy membership function solving is applied. Finally, the case studies show that the proposed operation framework reduces the economic operation cost by 28.29% and improves the WP utilization rate by 31.9%.

SRAM is crucial in cryptographic devices for temporarily storing secret keys used in encryption and decryption. However, conventional 6T SRAM cells are vulnerable to side-channel attacks (SCA) via power consumption analysis, as writing the same and opposite data consumes unequal power. Additionally, the Negative Bias Temperature Instability (NBTI) effect in PMOS transistors introduces a data imprinting attack, where attackers exploit differences in the relative strength of pull-up transistors, affecting the threshold voltage ($V_{\text{th}})$, noise margin (SNM), and delay of the SRAM cell, to retrieve stored data. To address these vulnerabilities, a new SRAM cell design is proposed, incorporating a loop cutting technique to prevent SCA and data toggling behavior to mitigate the data imprinting attack. Monte Carlo simulations of power dissipation during various write operations show that the proposed cell achieves a secure write operation with a maximum overlap of 96.87%. The loop cutting technique reduces power dissipation by 1.54 times and write operation time by 1.44 times compared to the conventional 6T SRAM cell. The stress factor (SF) is also calculated to measure the stress on storage nodes over time. The SF for the 6T SRAM cell is 2.34 after 180 min, while the data toggling approach in the proposed SRAM cell achieves an SF of 0.72, effectively preventing the data imprinting effect. The introduction of transmission gates increases the area overhead of the proposed cell by 1.88$\times$. All simulations are conducted using the gpdk 90-nm technology file in Cadence Virtuoso.

Nowadays, intelligent industrial aquaculture management has been a more universal demand in digital society. Deep learning-based vision computing technique can provide much potential for such applications. As a result, this paper proposes a deep vision computation-driven realtime multitarget tracking approach for this purpose. It is a two-stage method, in which object detection is used in the first stage and target tracking is used in the second stage. First, the improved YOLOv7 model is utilized to train and identify the preprocessed data set to achieve accurate detection of fish targets. Then, a tracking algorithm, named SORT, is utilized to conduct an in-depth analysis of fish images to achieve continuous tracking of fish targets. Thus, further management affairs can be realized upon the basis of such conditions. Experimental results show that the improved YOLOv7 model achieves a high accuracy of 92% on the target detection task, and the Sort algorithm maintains a high degree of tracking accuracy and low tracking errors between consecutive frames. By combining these two methods, the daily behavior of fishes can be accurately detected and tracked in real time. In addition, the research also explores how to combine tracking results with breeding decisions to promote the development of breeding management in an intelligent direction.