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A FinFET-Based Low Leakage 10T Static Random Access Memory Cell

Anandita Srivastav

Department of EECE, Sharda University, Greater Noida, India

E-mail Address: ananditasrvstv19@gmail.com

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Usha Tiwari

Department of EECE, Sharda University, Greater Noida, India

E-mail Address: ushapant@rediffmail.com

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Sushanta K. Mandal

Department of Electrical and Electronics Engineering, ADAMAS University, Kolkata, India

E-mail Address: sushanta.mandal@gmail.com

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, and

Ashish Sachdeva

https://orcid.org/0000-0003-2434-5073

Department of Electronics and Communication, Maharishi Markandeshwar Engineering College, Maharishi Markandeshwar (Deemed to be University), Mullana, Ambala, India

E-mail Address: er.ashishsachdeva@gmail.com

Corresponding author.

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https://doi.org/10.1142/S0218126625500975Cited by:0 (Source: Crossref)

Abstract

In this work, a transmission gate-based low-power ten FinFET (TGLP10T) single-ended read/write SRAM cell is proposed. The proposed cell achieves low leakage operation along with improved write-ability. The performance metric results obtained from TGLP10T are compared with five previously published bit-cell designs, i.e., conventional 6T (Con6T), robust transmission gate-based 10T SRAM (RTG10T), transmission gate-based variation resistant 9T SRAM (TGVR9T), PNN (PMOS-NMOS-NMOS) inverter-based 10T (PNN10T) and PPN (PMOS-PMOS-NMOS) inverter-based read decoupled 10T (PPNRD10T. The leakage power in proposed design is reduced by $1.27 \times ∕ 1.15 \times ∕ 1.33 \times ∕ 1.15 \times ∕ 1.00 \times$ compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The write power and WSNM are improved by $1.07 \times ∕ 1.40 \times ∕ 0.87 \times ∕ 1.63 \times ∕ 0.78 \times$ and $1.57 \times ∕ 1.69 \times ∕ 1.08 \times ∕ 1.59 \times ∕ 1.50 \times ∕ 1.00 \times$ , respectively, compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The read delay and write delay are improved by $1.00 \times ∕ 1.54 \times ∕ 1.36 \times ∕ 1 \times ∕ 2.83 \times$ and 1.68 $\times ∕ 2.35 \times ∕ 1.82 \times ∕ 2.89 \times ∕ 1.77 \times$ , respectively, compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The proposed design shows the least data retention voltage compared to other SRAM bit-cells.

^∗ This paper was recommended by Regional Editor Giuseppe Ferri.

Keywords:

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