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Design of Low Power Half Select Free 10T Static Random-Access Memory Cell

Department of Electronics and Communication Engineering, Institute of Engineering and Technology, GLA University, Mathura 281406, India

E-mail Address: er.ashishsachdeva@gmail.com

Corresponding author.

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V. K. Tomar

Department of Electronics and Communication Engineering, Institute of Engineering and Technology, GLA University, Mathura 281406, India

E-mail Address: vinay.tomar@gla.ac.in

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https://doi.org/10.1142/S0218126621500730Cited by:26 (Source: Crossref)

Abstract

This paper presents a circuit-level technique of designing a low power and half select free 10T Static Random-Access Memory Cell (SRAM). The proposed cell works with single end read operation and differential write operation. The proposed bit-cell is free from half select issue and supports bit interleaving format. The presented 10T cell exhibits 40.75% lower read power consumption in comparison to conventional 6T SRAM cell, attributed to reduction of activity factor during read operation. The loop cutting transistors used in core latch improve write signal-to-noise margin (WSNM) by 14.94% and read decoupled structure improve read signal-to-noise margin (RSNM) by $2.02 \times$ $2.02 \times$ as compared to conventional 6T SRAM. In the proposed work, variability analysis of significant design parameters such as read current, stand-by SNM, and read power of the projected 10T SRAM cell is presented and compared with considered topologies. Mean value of hold static noise margin of the cell for 3000 samples is $1.75 \times$ $1.75 \times$ times higher than the considered D2p11T cell. The proposed 10T cell shows $1.83 \times$ $1.83 \times$ and $1.22 \times$ $1.22 \times$ narrower read access time and write access time, respectively, as compared to conventional 6T SRAM cell. Read current to bit-line leakage current ratio of the proposed 10T cell has been investigated and is improved by $2.75 \times$ $2.75 \times$ as compared to conventional 6T SRAM cell. The write power delay product and read power delay product of the proposed 10T cell are $4.21 \times$ $4.21 \times$ and $2.79 \times$ $2.79 \times$ lower than conventional 6T SRAM cell. In this work, cadence virtuoso tool with Generic Process Design Kit (GPDK) 45nm technology file has been utilized to carry out simulations.

This paper was recommended by Regional Editor Piero Malcovati.

Keywords:

References

1. E. Simmon, K.-S. Kim, E. Subrahmanian, R. Lee, F. De Vaulx, Y. Murakami, K. Zettsu and R. D. Sriram, A Vision of Cyber-Physical Cloud Computing for Smart Networked Systems (US Department of Commerce, National Institute of Standards and Technology, 2013). Crossref, Google Scholar
2. A. Sinha and A. Islam, Low-power half-select free single-ended 10 transistor SRAM cell, Microsyst. Technol. 23 (2017) 4133–4144. Crossref, Web of Science, Google Scholar
3. E. Morifuji, T. Yoshida, M. Kanda, S. Matsuda, S. Yamada and F. Matsuoka, Supply and threshold-voltage trends for scaled logic and SRSM MOSFETs, IEEE Trans. Electron Devices 53 (2006) 1427–1432. Crossref, Web of Science, Google Scholar
4. M. Nabavi and M. Sachdev, A 290-mV, 3.34-MHz, 6T SRAM with PMOS access transistors and boosted wordline in 65-nm CMOS technology, IEEE J. Solid-State Circuits 53 (2017) 656–667. Crossref, Web of Science, Google Scholar
5. G. Pasandi and S. M. Fakhraie, An 8T low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and finFETs, IEEE Trans. Electron Devices 61 (2014) 2357–2363. Crossref, Web of Science, Google Scholar
6. N. Maroof and B.-S. Kong, 10T SRAM using half-VDD precharge and row-wise dynamically powered read port for low switching power and ultralow RBL leakage, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25 (2016) 1193–1203. Crossref, Web of Science, Google Scholar
7. T. Azam, B. Cheng, S. Roy and D. Cumming, Robust asymmetric 6T-SRAM cell for low-power operation in nano-CMOS technologies, Electron. Lett. 46 (2010) 273–274. Crossref, Web of Science, Google Scholar
8. S. Pal, S. Bose, W.-H. Ki and A. Islam, Characterization of half-select free write assist 9T SRAM cell, IEEE Trans. Electron Devices 66 (2019) 4745–4752. Crossref, Web of Science, Google Scholar
9. S. Pal and A. Islam, Variation tolerant differential 8T SRAM cell for ultralow power applications, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 35 (2015) 549–558. Crossref, Web of Science, Google Scholar
10. M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa and T. Kawahara, Low-power embedded SRAM modules with expanded margins for writing, IEEE Int. Digest of Technical Papers. Solid-State Circuits Conf. 2005 (ISSCC 2005) (IEEE, 2005), pp. 480–611. Google Scholar
11. A. Islam and M. Hasan, Leakage characterization of 10T SRAM cell, IEEE Trans. Electron Devices 59 (2012) 631–638. Crossref, Web of Science, Google Scholar
12. S. Pal and A. Islam, 9-T SRAM cell for reliable ultralow-power applications and solving multibit soft-error issue, IEEE Trans. Device Mater. Reliab. 16 (2016) 172–182. Crossref, Web of Science, Google Scholar
13. N. Verma and A. P. Chandrakasan, A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy, IEEE J. Solid-State Circuits 43 (2008) 141–149. Crossref, Web of Science, Google Scholar
14. Y.-W. Chiu, Y.-H. Hu, M.-H. Tu, J.-K. Zhao, Y.-H. Chu, S.-J. Jou and C.-T. Chuang, 40nm bit-interleaving 12T subthreshold SRAM with data-aware write-assist, IEEE Trans. Circuits Syst. I, Regul. Pap. 61 (2014) 2578–2585. Google Scholar
15. L. Wen, Z. Li and Y. Li, Differential-read 8T SRAM cell with tunable access and pull-down transistors, Electron. Lett. 48 (2012) 1260–1261. Crossref, Web of Science, Google Scholar
16. A. P. Chandrakasan and R. W. Brodersen, Minimizing power consumption in digital CMOS circuits, Proc. IEEE 83 (1995) 498–523. Crossref, Web of Science, Google Scholar
17. S. Gupta, K. Gupta and N. Pandey, A 32-nm subthreshold 7T SRAM bit cell with read assist, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25 (2017) 3473–3483. Crossref, Web of Science, Google Scholar
18. H. Farkhani, A. Peiravi and F. Moradi, A new asymmetric 6T SRAM cell with a write assist technique in 65nm CMOS technology, Microelectron. J. 45 (2014) 1556–1565. Crossref, Web of Science, Google Scholar
19. R. E. Aly and M. A. Bayoumi, Low-power cache design using 7T SRAM cell, IEEE Trans. Circuits Syst. II Express Briefs 54 (2007) 318–322. Crossref, Web of Science, Google Scholar
20. S. Pal, V. Gupta, W. H. Ki and A. Islam, Transmission gate-based 9T SRAM cell for variation resilient low power and reliable internet of things applications, IET Circuits Devices Syst. 13 (2019) 584–595. Crossref, Web of Science, Google Scholar
21. J. P. Kulkarni, K. Kim and K. Roy, A 160mV robust Schmitt trigger based subthreshold SRAM, IEEE J. Solid-State Circuits 42 (2007) 2303–2313. Crossref, Web of Science, Google Scholar
22. C.-H. Lo and S.-Y. Huang, P-P-N based 10T SRAM cell for low-leakage and resilient subthreshold operation, IEEE J. Solid-State Circuits 46 (2011) 695–704. Crossref, Web of Science, Google Scholar
23. V. Sharma, M. Gopal, P. Singh, S. K. Vishvakarma and S. S. Chouhan, A robust, ultra low-power, data-dependent-power-supplied 11t SRAM cell with expanded read/write stabilities for internet-of-things applications, Analog Integr. Circuits Signal Process. 98 (2019) 331–346. Crossref, Web of Science, Google Scholar
24. A. Sachdeva and V. Tomar, Design of a stable low power 11-T static random access memory cell, J. Circuits Syst. Comput. (JCSC) 29(13) (2020) 2050206, https://doi.org/10.1142/S0218126620502060. Link, Web of Science, Google Scholar
25. S. Pal, S. Bose, W.-H. Ki and A. Islam, A highly stable reliable SRAM cell design for low power applications, Microelectron. Reliab. 105 (2020) 113503. Crossref, Web of Science, Google Scholar
26. S. K. Saha, Compact MOSFET modeling for process variability-aware VLSI circuit design, IEEE Access 2 (2014) 104–115. Crossref, Web of Science, Google Scholar
27. A. Islam and M. Hasan, A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM cell, Microelectron. Reliab. 52 (2012) 405–411. Crossref, Web of Science, Google Scholar
28. E. Seevinck, F. J. List and J. Lohstroh, Static-noise margin analysis of MOS SRAM cells, IEEE J. Solid-State Circuits 22 (1987) 748–754. Crossref, Web of Science, Google Scholar
29. K. Takeda, H. Ikeda, Y. Hagihara, M. Nomura and H. Kobatake, Redefinition of write margin for next-generation SRAM and write-margin monitoring circuit, 2006 IEEE Int. Solid State Circuits Conf. — Digest of Technical Papers (IEEE, 2006), pp. 2602–2611. Google Scholar
30. N. Gierczynski, B. Borot, N. Planes and H. Brut, A new combined methodology for write-margin extraction of advanced SRAM, 2007 IEEE Int. Conf. Microelectronic Test Structures (IEEE, 2007), pp. 97–100. Crossref, Google Scholar
31. K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng and M. Bohr, A 3-GHz 70-MB SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply, IEEE J. Solid-State Circuits 41 (2005) 146–151. Crossref, Web of Science, Google Scholar
32. J. Wang, S. Nalam and B. H. Calhoun, Analyzing static and dynamic write margin for nanometer SRAMs, Proc. 13th Int. Symp. Low Power Electronics and Design (ISLPED’08) (IEEE, 2008), pp. 129–134. Crossref, Google Scholar
33. S. Dasgupta et al., Compact analytical model to extract write static noise margin (WSNM) for SRAM cell at 45-nm and 65-nm nodes, IEEE Trans. Semicond. Manuf. 31 (2017) 136–143. Web of Science, Google Scholar
34. J. Singh, S. P. Mohanty and D. K. Pradhan, Robust SRAM Designs and Analysis (Springer Science & Business Media, 2012). Google Scholar
35. S. Ahmad, M. K. Gupta, N. Alam and M. Hasan, Low leakage single bitline 9T (SB9T) static random access memory, Microelectron. J. 62 (2017) 1–11. Crossref, Web of Science, Google Scholar
36. H. Qin, Y. Cao, D. Markovic, A. Vladimirescu and J. Rabaey, Standby supply voltage minimization for deep sub-micron SRAM, Microelectron. J. 36 (2005) 789–800. Crossref, Web of Science, Google Scholar
37. S. Dasgupta et al., 6T SRAM cell analysis for DRV and read stability, J. Semicond. 38 (2017) 025001. Crossref, Web of Science, Google Scholar
38. R. Gupta and S. Dasgupta, Process corners analysis of data retention voltage (DRV) for 6T, 8T, and 10T SRAM cells at 45nm, IETE J. Res. 65 (2019) 114–119. Crossref, Web of Science, Google Scholar
39. S. M. Jahinuzzaman, M. Sharifkhani and M. Sachdev, An analytical model for soft error critical charge of nanometric SRAMs, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17 (2009) 1187–1195. Crossref, Web of Science, Google Scholar
40. G. Pasandi and M. Pedram, Internal write-back and read-before-write schemes to eliminate the disturbance to the half-selected cells in SRAMs, IET Circuits Devices Syst. 12 (2018) 460–466. Crossref, Web of Science, Google Scholar