Journal of Circuits, Systems and Computers

This work presents a behavior-based memristor model for the simulation of novel digital logic architectures. This model exhibits the nonvolatile hard switching current–voltage curves of the experimentally realized memristors. Because the model is implemented via the widely available traditional SPICE (Simulation Program with Integrated Circuit Emphasis) circuit components, its accuracy is not dependent on still-emerging device transport theory and auxiliary variables. The memristor model is used in material implication (IMPLY) gates to perform both combinational and sequential logics. As IMPLY gates exhibit the complete functionality required for digital logic, this work presents a simple realistic memristor model for use in the simulation of novel digital logic architectures.

The demand for visual quality has been advanced by high display resolutions and frame rates. Nevertheless, these two issues have caused tremendous memory bandwidth in a video coding system. In this study, an efficient lossless embedded compression (EC) algorithm is proposed to save memory bandwidth, while keeping visual quality. The proposed lossless EC algorithm incorporates three core techniques: tree partition, half-pixel prediction and group-based binary coding. Tree partition classifies a $16\times 8$ block into Trunk, Branch and Leaf. With tree partition, half-pixel prediction produces individual residues for Trunk, Branch and Leaf. Group-based binary coding converts theses residues to efficient codewords. The lossless compression ratio (CR) of the proposed EC is as high as 2.24 on average, saving memory bandwidth by 55.4%. This EC algorithm is implemented using CMOS 0.18$\mu$m technology. The maximum throughput can reach 6.4Gpixels/s, which can accommodate 3840 × 2160@60fps. The experiment results demonstrate that this study presents better hardware efficiency of 337Gpixels/J and 83.5Kpixels/s/gate.

Cognitive radio network (CRN) is considered to be the future technology for the fifth generation of cellular wireless standards (5G). CRN is based on a complex spectrum allocation system, and licensed primary users (PUs) or unlicensed secondary users (SUs) are allowed to share the spectrum, provided that they do not cause significant interference. In cognitive radio, it is important to control the transmission power of SUs so that the interference should not be harmful to the quality of service of PUs. In this paper, the authors addressed the impact of system imperfections on the overall performance of multi-carrier code division multiple access (MC-CDMA)-based CRN system. A new expression of the signal-to-interference-noise ratio (SINR) for MC-CDMA-based CRN system over a Rayleigh fading channel without any power control condition among the PUs and SUs is derived and investigated. The performance of MC-CDMA-based CRN system over the frequency selective multi-path fading channel is examined by varying the number of users, the signal-to-noise-ratio (SNR) per bit, number of fading path and number of subcarriers, respectively. From the simulation results, we have seen that the SINR performance is affected by these parameters. The analysis presented in this paper shows the impact of lack of a controlling mechanism on transmitted signal power affecting the between PUs and SUs ultimately system performance. The result of the analysis will provide relevant information to design the physical layer protocol for high speed CRN system for 5G.

Most of today’s IoT-based computing systems offer an opportunity to build smarter systems for application areas such as healthcare monitoring and wireless sensor nodes. Since these systems are energy limited and remain idle for most of the time, they suffer from large leakage power dissipation. Another problem faced by such computing systems is sporadic power failures when employed with energy harvesters where the system loses its current state and needs long reinitialization time. To address these problems, this work combines asynchronous design techniques with nonvolatility to achieve ultra-low power operation during active mode and data retention during power failure. This paper first presents a detailed analysis of different implementations of volatile c-element and compares their performance in terms of power and delay. Then one of the implementations is selected for nonvolatile design of a hybrid c-element using emerging spin transfer torque–magnetic tunnel junction (STT–MTJ) technology which allows energy-efficient data retention during idle mode/power-off mode and during sudden power failures. Using this hybrid c-element, we design a novel nonvolatile weak conditioned half-buffer. The extensive analysis of these designs with different design metrics is performed at the circuit level using Synopsys HSPICE circuit simulator.

Distributed cameras have been used widely for real-time image recognition. There are two main approaches in distributed camera systems: (1) The cameras are equipped with a powerful high-end processor for local image processing, (2) Low-cost cameras with resource-constrained processors are used for capturing the images and transferring them to a cloud server for classification purposes. The first approach is costly and not scalable. The second approach is too slow for real-time object detection due to the transfer delays to a remote server. These problems exacerbate in multi-view image recognition, where a central platform is required for collective image processing of multiple images from the same scene. For this purpose, typically, a cloud server is used, which does not meet real-time recognition, network bandwidth, scalability and power consumption constraints of such systems. This paper proposes hierarchical neural network structures that can be realized in an edge orchestration architecture at different levels, i.e., cameras, edge devices, and cloud servers to enable deep learning capabilities for real-time multi-view image recognition. This would enable us to detect objects in the proximity of multiple cameras and transfer data for deeper layer processing to the cloud server and training of all connected edge devices and cameras.

This paper presents a new topology of single-stage inverter to generate quality sinusoidal output waveform without any additional boosting components. The proposed inverter is a combination of back-to-back two Cuk converters and hence, it is named as a cuk inverter. As per the inductor value, it can operate in continuous and discontinuous current mode. The sinusoidal output voltage can be raised or lowered with different duty ratio based on the load requirement. This Cuk inverter reduces the filter requirement in the output circuit. Further, to show the advantage of the proposed topology, a comparative study is carried out with conventional and recent converters in terms of number of switches, LC components and applications. The performance of the proposed topology is analyzed with MATLAB/Simulink tool and implemented as hardware to validate the simulated results.

This work describes a new scheme for denoising noisy electrocardiogram (ECG) signals. In the first step, the noise variance is estimated using the well-known DONOHO’s estimator followed by the wavelet-based baseline wander removing. In the second step, the estimated variance is employed in the adaptive 1D Wiener filter to reduce the additive noise. Next, a Low Pass filter, based on the FFT, is applied on the resulting denoised signal. Furthermore, a cascaded Savitzky–Golay (SG) smoother filter is applied to refine the restoration process. The final step consists in the recovering of the $R$-peaks and the surrounding areas. It can be reported that the suggested algorithm is optimal for the additive Gaussian noise and is useful for other types of noises. Both qualitative and quantitative results, achieved from several experimental tests, establish high-quality restoration ability and the efficiency of the proposed method. Thus, when compared to some powerful techniques recently published, the designed algorithm demonstrates very competitive performances.

Today, field programmable gate array (FPGA) is becoming widely used as computational accelerators in many application domains such as image/video processing, machine learning, and data mining. The inherent tolerance to the imprecise computation in such domains potentially provides an opportunity to trade quality of the results for higher energy efficiency. Therefore, this paper proposes a systematic methodology aiming to find the optimal energy saving corresponding to different quality bound, by approximating register-transfer level (RTL) designs on FPGA. As a case study, first, we investigate imprecise design on two submodules — adders and multipliers. By integrating the two combinational submodules with finite state machines (FSMs), several designs on a sequential circuit — color-to-grayscale converter — are further presented to offer a diverse range of energy consumption related to different quality constrains. Through this, we are able to set energy–quality (E–Q) parameters of our proposed methodology and configure the approximation knobs, capable of maximizing energy savings within different application-based quality margins. Experimental result demonstrates that leveraging E–Q leads to an average $1.37$–$2.16\times$ savings in energy for modest loss in application output quality ($<3\%$), and $2.31$–$2.50\times$ energy savings for impact on relaxed quality constraints (3–7.5%).

Wireless Sensor Networks (WSNs) are used for data collection from the surrounding environment using the enormous amount of sensor nodes. Energy saving is the most fundamental challenge of WSNs which primarily depends on the Cluster Head (CH) selection and packet routing strategy. In this paper, we are proposing an Energy Aware Distance-based Cluster Head selection and Routing (EADCR) protocol to extend the lifetime of WSN using the FCM technique, residual energy of the nodes, their relative Euclidean distances from the Base Station (BS) and cluster centroid. Since the nodes consume a considerable amount of energy during the clustering phase, thus to avoid this, here, we are introducing a new clustering approach where the CH selection is now based on the newly proposed fitness function. We are also providing a new strategy for packet routing using the shortest path technique for routing between node and its destination which reduces the energy consumption of the CHs by employing the multi-hop communication. We also save the energy of the nodes using their Euclidean distances among them, from their CH and from BS. The simulation results exhibit that the EADCR enhances the network lifetime as compared to the other similar algorithms, e.g., FCM, REHR, UCRA–GSO and CCA–GWO under different scenarios. It also saves the residual energy of the network and enhances the network coverage.

In this paper, Lagrangian-based method has been proposed for tuning the parameters of fractional order $P{I}^{\alpha }{D}^{\beta }$ controller. In this method, the five parameters ($K_p$, $K_i$, $K_d$, $\alpha$ and $\beta$) of fractional order $P{I}^{\alpha }{D}^{\beta }$ controller (FOPID) are suitably optimized, and successfully applied to a benchmark stable second-order feedback system. To prove the performance of the proposed method, several state-of-the-art approaches were compared. The computational complexity, robustness and stability analysis has been performed to investigate the performance of all these algorithms. Moreover, the precision and flexibility analysis among all these approaches has also been carried out in this paper. The closed loop response of the second-order bench mark stable plant in Simulink has also been depicted in this paper.

An Application Specific Inflexible FPGA (ASIF) is a tailored design, for a given group of known circuits, which is generated by extensively reducing the routing resources of an FPGA. In an ASIF, different dynamically reconfigurable application circuits are initially mapped and tested on an FPGA fabric. Subsequently, the FPGA fabric is reduced to achieve an efficient architecture for known application circuits. However, a large portion of ASIF is still occupied by fully flexible logic blocks, containing the same amount of area and SRAM memory cells, as found in a traditional FPGA. Thus, here lies a potential to further optimize the logic blocks of an ASIF at the expense of removing or reducing their reconfigurability. This work optimizes the logic blocks of an ASIF through the SRAM-Table sharing technique, without compromising their reconfigurability. Moreover, the routing channels of ASIF are further optimized by applying the Boolean functions (Gates) insertion technique. The applied techniques (SRAM-Table sharing and Boolean functions insertion) not only reduce the area, delay and power, but also minimize the reconfiguration time, bitstream size and the size of external memory required to store the bitstream of circuits. This optimized version of ASIF is termed as ASIF$++$. Furthermore, an embedded FPGA in a System-on-Chip that requires the partial dynamic reconfiguration for known circuits, can be automatically reduced to an ASIF$++$. It is found through experimental results that an ASIF$++$ is 4–9$\%$ area-efficient and requires $36\%$ lesser number of SRAM cells, as compared to the previously proposed ASIF for a group of 2–5 circuits. It also achieves 34–53$\%$ area saving as compared to a traditional FPGA.

Experimental study is presented to uncover entrainment property of Pierce oscillator circuit (i.e., one of the most standard circuits for crystal oscillators) subject to sinusoidal external forcing. In contrast to the well-known Arnold tongues observed in a wide class of forced nonlinear systems, asymmetric shape was observed as an entrainment region of the circuit in two-dimensional parameter space spanned by the external forcing strength and frequency. Computation of the impedance curve revealed that the asymmetric shape is due to positive (inductive) or negative (capacitive) reactance of the Pierce circuit, which facilitates or inhibits the circuit oscillations. We extend this insight into two coupled Pierce circuits and show that, to efficiently achieve their synchronization, it is advantageous to drive a slow oscillator circuit by a fast circuit rather than to drive a fast circuit by a slow circuit. Our study provides a guideline on an optimal network configuration for coupled crystal oscillators, which may find applications in distributed digital clocks and wireless communication systems.

This paper deals about the development of intelligent controllers (ICs) for load voltage regulation of a double switch noninverting buck-boost DSNIBBC operated in pseudo continuous coil current (PCCC). The DSNIBBC is a kind of DC-DC converter, which converts the positive DC source voltage into the positive DC load voltage (buck to boost mode and boost to buck mode). Due to the time changing, ON/OFF characteristics along with its transient and dynamic characteristics of DSNIBBC have become nonlinear. Since the classical linear controllers are inappropriate to enhance the transient and dynamic performances of DSNIBBC, ICs are designed to improve the load control of the same DSNIBBC operated in transient and dynamic regions. In this paper, two ICs, namely, fuzzy logic controller (FLC) and neuro controller (NC) incorporated in the load voltage regulation loop are utilized. The performance comparison between the ICs and the classical proportional integral (PI) controller is discussed and validated at various regions through both software and prototype field programmable gate array [FPGA] plants. The responses are depicted to support the designed ICs.

Serial ensemble Kalman filter (EnKF) is a kind of EnKF which treats observations serially during every assimilation step. The assimilation order can be generated by different rules and has significant impacts on the performance of serial EnKF when localization algorithm is applied. In this study, we seek to examine and better understand the characteristics of various ordering methods when they are applied in the serial EnKF. The results show that different ordering methods demonstrate almost the same changes in analysis as the localization radius changing. Moreover, the optimal parameters of localization radius and forgetting factor of serial EnKF are found varying among different ordering rules. In addition, a novel rule for confirming the assimilation order is proposed to further improve the performance of serial EnKF. The observations are sorted from “better” to “worse” (OBS-BtoW), which are evaluated by estimating the distance of analysis between the prior and observations. Compared with the existing ordering methods, the proposed method can improve the performance at a very small computation cost without needing future forecasts and the truth.

Several application-specific processor design approaches have been proposed and investigated to cope with the emerging flexibility requirements jointly associated with the maximum performance efficiency and minimum implementation area and power consumption. Dynamic scheduling of a set of instructions generally leads to an overhead related to instruction decoding. To mitigate this overhead, other approaches have been proposed using static scheduling of datapath control signals. In this context, No-Instruction-Set-Computer (NISC) concept have been introduced considering that a dedicated processor to a specific application does not need an instruction set especially when it is programmed by its designers and not by its users. In this paper, the hardware architecture design of flexible NISC-based architecture design dedicated for minimum mean-squared error (MMSE) linear detection is presented. The devised design, which is used in iterative turbo-receiver, fulfills the performance requirements of emergent wireless communication standards with throughput reaching that of LTE-Advanced. FPGA hardware implementation of the detector architecture achieves a maximum throughput of 115.8 Mega symbols per second for $2\times 2$ and 6.4 Mega symbols per second for $4\times 4$ MIMO systems for an operating clock frequency of 202.67MHz.

In this paper, a method is presented for the mathematical modeling and analysis of the DC–DC Buck Converter output voltage. This paper consists of the demonstration of a mathematical model for the converter transient response submitted to a pulse width modulated (PWM) input voltage, resulting in accurate symbolic expressions for the output voltage. The novelty of the method is the capability of the expressions derived to describe correctly the behavior of the converter submitted to time-varying control reference input signals modulating the switch pulse width. The mathematical model was then validated by comparing it with the responses obtained using the Runge–Kutta numerical method. By using different circuit parameters and PWM input signals with constant and time-varying duty cycles, it was possible to validate the model for different cases, showing the effectiveness of the approach.

Developing an analog-to-digital converter (ADC) based on the time-interleaved delta–sigma modulator (TIDSM) is an appropriate technique to attain high-speed ADCs. TIDSMs can be successfully accomplished with the aid of developing the block digital filtering (BDF) method. In this approach, $M$ mutually cross-connection delta–sigma modulators are used, whereby each one of them operates at a sampling rate of $f_s$, leading to an effective sampling rate of ${M\ast f}_s$. In this study, a novel structure is proposed based on the Noise Coupled time-interleaved delta–sigma modulator (NC-TIDSM) with reduced hardware complexity. This structure not only increases the overall noise transfer function (NTF) order, but also reduces the hardware element counts. The simulation results demonstrate that the SNDRs of the first-order two-channel and four-channel NC-TIDSM with reduced hardware are 13 and 15 dB better than those of their BDF technique counterparts; also, the SNDR of the second-order two-channel NC-TIDSM with reduced hardware is 8 dB better than that of their BDF technique counterpart; also, the hardware element quantities are reduced dramatically. Moreover, some practical challenges such as the finite op-amp’s gain and mismatching effects that directly affect the circuit implementation of the proposed structure have been described. Furthermore, the hardware complexity of the proposed structures is reduced considerably in comparison to that of the BDF technique with the NC-TIDSM structure.

Symmetry is not only used to simplify the analysis of three-phase electrical systems, but it is also used to define its voltages, currents and loads. When the loads are symmetrical, the currents of a three-phase AC system are expected to be symmetrical as well. Given the proper conditions, in converters such as the matrix converter (MC), the output voltages and currents are expected to be sinusoidal with periodic symmetry. However, in some cases this symmetry is broken so that, there appears nonlinear behaviors such as quasiperiodicity and so on. Based on simulations and experiments, this paper focuses on an analysis of a quasiperiodic behavior and the presence of a DC component in the output currents of a Venturini modulated MC. The presence of such behaviors in the output currents indicates that the symmetry in a period is broken. The broken symmetries appear when the input and output frequencies are mismatched. In addition, this paper shows the possibility to recover the symmetry of the output currents of the MC. The method for symmetry recovery is based on a time-delayed feedback control. The simulation and experimental results indicate the possibility of attenuating the quasiperiodic behavior and DC component.

This paper presents a circuit-level technique of designing a low power and half select free 10T Static Random-Access Memory Cell (SRAM). The proposed cell works with single end read operation and differential write operation. The proposed bit-cell is free from half select issue and supports bit interleaving format. The presented 10T cell exhibits 40.75% lower read power consumption in comparison to conventional 6T SRAM cell, attributed to reduction of activity factor during read operation. The loop cutting transistors used in core latch improve write signal-to-noise margin (WSNM) by 14.94% and read decoupled structure improve read signal-to-noise margin (RSNM) by $2.02\times$ as compared to conventional 6T SRAM. In the proposed work, variability analysis of significant design parameters such as read current, stand-by SNM, and read power of the projected 10T SRAM cell is presented and compared with considered topologies. Mean value of hold static noise margin of the cell for 3000 samples is $1.75\times$ times higher than the considered D2p11T cell. The proposed 10T cell shows $1.83\times$ and $1.22\times$ narrower read access time and write access time, respectively, as compared to conventional 6T SRAM cell. Read current to bit-line leakage current ratio of the proposed 10T cell has been investigated and is improved by $2.75\times$ as compared to conventional 6T SRAM cell. The write power delay product and read power delay product of the proposed 10T cell are $4.21\times$ and $2.79\times$ lower than conventional 6T SRAM cell. In this work, cadence virtuoso tool with Generic Process Design Kit (GPDK) 45nm technology file has been utilized to carry out simulations.

The growing complexity of modern digital design makes designers shift toward starting design exploration using high-level languages, and generating register transfer level (RTL) design from system level modeling (SLM) using high-level synthesis tools or manual transformation. Unfortunately, this translation process is very complex and error prone. The most important verification task is to check whether the RTL implementation is indeed equivalent to the system-level model. Equivalence checking is critical to ensure that the synthesized RTL conforms to its SLM specification.

In this paper, we propose a novel path-based sequential equivalence checking method to validate the transformed RTL description against its corresponding SLM description. We represent the original SLM and the transformed RTL descriptions using Finite state machines with datapath (FSMD) and compare the path-pairs of the FSMD to obtain the equivalence of the designs. Then we recognize the corresponding path-pairs from all the generated paths of FSMD with Machine learning (ML) technique, and compare the recognized path-pairs by symbolic simulation and a satisfiability modulo theories (SMT) solver. Our method can handle designs without mapping information and improve the efficiency of the state-of-the-art path-based equivalence checking methods. The promising experiments on representative benchmarks indicate the efficiency and effectiveness of our method.