Journal of Circuits, Systems and Computers

In digital signal processing (DSP), the most valuable elements of processing architecture are multiplier. The conventional partial products array is to create extra rows and columns. Generally, the fixed multiplication products are truncated to $m$ bits. In this paper, we introduced an adaptive booth multiplier concept, which is based on truncated multiplication procedure. The extra partial product array is to create the complexities. In the higher order of partial product array, the deletion of LSB and the nongeneration of initial products are achieved. We added compensation bits at the appropriate retained bit position to minimize the error due to nongeneration and omission. Here, our proposed work is used to reduce the overhead and the complexity of partial product array. The proposed concept architecture is implemented in Verilog HDL software; also the design of RTL is manufactured. For experimental work, the bit multiplication of $8\times 8$ with 8, 10, 12, 14 and 16 bits is used. The proposed method of truncated based adaptive booth encoding has shown the lower value results of area, delay and power consumption. The error performances are executed by various error normalizations. Finally, the proposed concept performance is checked with various state-of-art multiplier methodologies such as carry width multiplier, Vedic multiplier, voltage-mode multiplier and Wallace multiplier. In every bit value, the proposed booth encoding multiplier delivers better and optimal performance result.

RSA-CRT is one of the most common algorithms in the digital signature. Several side-channel attacks have been presented on the implementation of RSA-CRT. One of the most important side-channel attacks on RSA-CRT is Modular Reduction on Equidistant Data (MRED). The implementation of RSA-CRT has too many challenges in the multiplications when the key size is too long (e.g. 2048 bits). Montgomery multiplication is one of the common methods for executing the RSA multiplication, which has many implementation problems and side-channel leakage challenges. This article first implements an RSA-CRT algorithm based on the Montgomery multiplication with the high-speed and low area hardware. The implementation is named RSA-CRT-MMB (Montgomery Method Based). Next, a new power analysis side-channel attack on RSA-CRT-MMB is presented. We name our attack MRED on MMB. The attack utilizes new side-channel leakage information about the CRT reduction algorithm implemented by the MMB, for the first time. The previous articles do not investigate the MRED attack on Montgomery multiplication in RSA-CRT. Finally, a new countermeasure is presented to prevent the MREDM attack. The countermeasure does not have any overload in the hardware area or running time of the RSA algorithm. The correctness of our scheme, the 2048-bit RSA-CRT-MMB, is investigated by the implementation of the scheme on the SASEBO-W board in our DPA laboratory. The total running time of 2048-bit RSA is 250ms and the RSA algorithm occupies only 23% of LUT slice on Spartan-6 FPGA. The proposed countermeasures are also verified by practical experiments.

Dynamic voltage instability is one of the major issues faced by grid-connected renewable energy systems due to fluctuations in the generation and sudden variation in the loads. The primary objective of this paper is to propose a method for constant power consumption from the grid to maintain a stable DC-link voltage during peak and nonpeak hours. It can be achieved by implementing an optimized active power management (OAPM) scheme between the photovoltaic (PV) and the grid by enabling a battery energy storage system (BESS). The intelligent constant power balance (ICPB) algorithm and detailed control strategies for dual active bridge (DAB) isolated DC–DC converter and grid-connected voltage source inverter (VSI) are discussed in this paper. Moreover, the high-gain step-up DC–DC converter (HSDC) is utilized to perform maximum power point tracking (MPPT) operation and to meet the required DC-link voltage. The accuracy of power transmission of DAB gets improved by imposing a curve-fitting interpolation (CFI) approach, thereby maintaining a constant DC-link voltage. Furthermore, an instantaneous sinusoidal current control (ISCC) scheme assures the feeding of active power with better power quality. The measured results are obtained and verified under different dynamic conditions of load and generation. Based on the validation, we conclude that the proposed OAPM scheme is most suitable for grid-connected renewable energy systems in the rural electrified microgrid.

This paper presents noise reduction and modified asynchronous logic regulation techniques used in successive approximation register (SAR) analog-to-digital converter (ADC). With a transconductance enhanced structure, noise reduction is provided in the dynamic comparator. The input referred noise of the proposed comparator is about 165$\mu$V rms at 60^∘C (typical corner). An enhanced-positive-feedback loop is introduced to reduce the regeneration delay of the comparator. In addition, a modified asynchronous logic regulation technique is exhibited, a clock with adaptable delay is driving the comparator in approximation phase. Consequently, the settling accuracy of DAC (Digital-to-Analog Converter) is enough and the conversion speed of SAR ADC is increased without any redundant cycles. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 4mW from 1.2V power supply with a $\mathrm{\text{SNDR}}>66.7$dB and $SFDR>82.1$dB. The proposed ADC core occupies an active area of 0.048mm², and the corresponding FoM is 27.2fJ/conversion-step at Nyquist rate.

Consuming energy at the maximal level is a major concern in wireless sensor networks (WSNs). Many researchers focus on reducing and preserving the energy. The duration of active network of WSNs is affected by energy consumption of sensor nodes. For typical applications such as structure monitoring, border surveillance, integrated into the external surface of a pipeline, and clambered along the sustaining structure of a bridge, sensor node energy efficiency is an important issue. The paper proposed an energy-efficient multi-hop routing protocol using hybrid optimization algorithm (E²MR-HOA) for WSNs. The proposed routing protocol consists of two algorithms, i.e., hybrid optimization algorithm. We present modified chemical reaction optimization (MCRO) algorithm to form clusters and select cluster head (CH) among the cluster members. Then the modified bacterial forging search (MBFS) algorithm is used to compute reliable route between source to destination. The proposed E²MR-HOA protocol is evaluated using NS2 simulations. The simulation result shows that the proposed routing protocol provides significant energy efficiency with network lifetime over the existing routing protocols.

Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows reconfiguration of some of the logic at runtime while the rest of the logic keeps operating. This feature allows the designers to build complex systems such as Software-Defined Radio (SDR) in a reasonable area. New issues can arise due to usage of DPR technique such as guaranteeing proper connections for the ports of the Reconfigurable Modules (RMs) which share the same Reconfigurable Region (RR) on the FPGA, waiting for running computations on a module before reconfiguring it, isolation of the reconfigurable modules during the reconfiguration process, and initialization of the reconfigurable module after the reconfiguration process is done. Also, the Clock Domain Crossing (CDC) verification of the dynamically reconfigurable systems is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. This paper summarizes our previous work to address these verification challenges for DPR. The approaches are demonstrated on a SDR system to show the effectiveness of applying these approaches in the design cycle.

This paper presents the solar powered charging control of lithium-ion battery. The flyback converter is used to extract the maximum power from the solar photovoltaic (PV) array and charge the battery. This paper also presents the fuzzy logic-based battery management system to protect the batteries due to overcharging and over-discharging conditions. The proposed method is designed and developed in the MATLAB/Simulink platform. Solar PV powered battery system is tested for step change in irradiance conditions and corresponding results are measured and analyzed. The effectiveness of the fuzzy logic-based battery management system is also presented. The simulation model for BMS technique has overall efficiency of 95.1%. In order to verify the effectiveness of the proposed system, experimental verification of the proposed method is implemented in real time and compared with simulation results.

Independent component analysis (ICA) is an efficient blind source separation technique, but the extracted independent components are randomly permuted in classic ICA algorithms, and subsequent identification is required to find the desired component. Such a two-stage method causes inefficiency. By utilizing the prior information, ICA with reference (ICA-R) algorithm can extract the desired source signal in one stage without subsequent processing. There are many theoretical extensions on ICA-R, but few hardware implementations can be found. Therefore, the efficient VLSI design of a fast one-stage independent component extracting system based on ICA-R algorithm is presented in this paper. The proposed system consists of Preprocess module and Iteration module, which are designed highly parallel and pipelined to accelerate the extraction process. The designed system is implemented in Kintex-7 FPGA, and its performance is verified using synthesized signal. Experiment results show that the presented system can extract the desired components in one stage without subsequent identification, and the highly parallel circuit structure of the system speeds up the component extracting process by $3.8\times$ compared to software implementation.

A new analog four-quadrant multiplier in CMOS technology is proposed using translinear loops (TLs). The novelty of the work includes an improved structure resulting in high precision output, low power consumption and low body effect error. The higher accuracy is achieved using a symmetrical arrangement of the proposed multiplier, where the errors on the two sides of circuit are subtracted from each other. The simple structure, as well as the sharing bias branch in the squaring circuits, leads to the low power dissipation of the multiplier circuit. In addition, the proposed circuit is thoroughly analyzed in terms of the body effect error and the results are presented. In order to validate the performance of the circuit, the designed multiplier is used in two useful applications: frequency doubler and amplitude modulator. The post layout simulation results of the circuit are performed using Cadence Virtuoso and HSPICE with level 49 parameters (BSIM3v3) of TSMC 0.18$\mu$m technology. The results show a nonlinearity of 0.93%, a total harmonic distortion (THD) of 0.98% at a frequency of 1MHz, a $-$3dB bandwidth of 736MHz and a maximum power dissipation of 0.0619mW.

The standardized communication protocol and the universal application of intelligent electronic devices in edge networks provide technical support to the realization of smart cities and also bring network security issues that cannot be ignored. How to analyze and quantitatively assess the vulnerability of the edge network has become an important issue that needs to be solved urgently in the edge network security risk control. Based on the analysis of the vulnerability mechanism, this paper proposes the selection criteria and generation methods of vulnerability indicators and of composite vulnerability indicators, respectively. In addition, this paper proposes an improved vulnerability severity rating method to analyze the vulnerability of the system and potential security threats. This paper describes the security risk status of vulnerable points based on the state transition of the state offensive and defensive graph and implements the description of the security risk status of attacks in terms of attack frequency, attack success rate and harm. Experimental results justify the effectiveness of the proposed solution.

This paper proposes a three-stage coarse-fine-tuning analog-assisted digital low dropout regulator (AAD-LDO) without digital ripple. The digital regulation consists of two stages, which break the accuracy-speed-power trade-off. To further improve transient response, a step-variable counter used in the first stage is designed, which makes sure that the output current can track the load current rapidly. The ripple caused by the digital regulation disappears due to the existence of the analog-assistant stage (in the proposed AAD-LDO). As a result, the AAD-LDO achieves the output voltage with high accuracy. Designed in a 0.18$\mu$m CMOS process, the proposed AAD-LDO has a layout area of 0.133mm. For the input range of 1.2–1.8V, the output voltage is 1V. The maximum load current is 10mA at the input voltage of 1.2V. The linear regulation and load regulation are 0.061mV/V and 0.0082mV/mA, respectively. The over/undershoot is suppressed effectively for a 9.5mA load step. The peak current efficiency is 99.78%.

Fault isolation in electronic circuits is a trending area of interest as analog circuits find valuable application in industry. The failures in circuit systems cause severe issues in the normal functioning of the system that insists on the need for an automatic method of fault isolation in analog circuits. Literature conveys the issues associated with the fault isolation and hence, to address the severity of the faults, a novel model is proposed to isolate the fault causing component in the circuit. The proposed Multi-Rider Optimization-based Neural Network (M-RideNN) isolates the faulty part of the circuit from the fault-free areas such that the fault diagnosis is structured in an effective way. The fault isolation is progressed as four major steps such as establishing the fault dictionary, signal normalization using Linear Predictive Coding (LPC), effective dimensional reduction methodology using Probabilistic Principal Component Analysis (PPCA), and fault isolation using the proposed M-RideNN classifier. Finally, the experimentation using three circuits, namely Triangular Wave Generator (TWG), Bipolar Transistor Amplifier (BTA), differentiator (DIF), and an application circuit, Solar Power Converter (SPC), proves that the proposed M-RideNN classifier offers better classification accuracy of 93.18% with a minimum Mean Square Error (MSE) of 0.0682.

Due to the rapid developments in the field of electric vehicles (EVs), it is necessary to find the alternate source to power the EVs. The energy sources, such as fuel cell (FC) and solar photovoltaics (PV), are preferred; however, these sources produce low output voltage, and it is not sufficient to drive the EVs. The DC–DC converters are used to boost the voltage to the required voltage of the EVs; in addition, the EVs also require multiple output terminals to deliver the power to various parts of the system. Hence, in this paper, a new DC–DC converter topology is proposed to produce the three different output voltages from the single input source. The proposed converter has features such as high voltage gain with less duty cycle, reduced number of components, less power loss, and hence the efficiency. Moreover, the converter is operated with a single MOSFET switch with low $R_{\mathrm{\text{ds-on}}}$ due to its less voltage stress and high voltage gain. The required voltage gain is achieved by the super-lift (SL) technique, and the converter is also provided with a passive clamp circuit to recover the leakage energy of the coupled inductor. The theoretical analysis of the proposed converter is verified through the experimental prototype of 300 W, and the result proves the converter may be suitable for EV applications and the applications which require multi-level output voltage with a high voltage gain.

Huge amount of personal data is collected by online applications and its protection based on privacy has brought a lot of major challenging issues. Hence, the $K$-anonymization with privacy-preserving data publishing has emerged as an active research field. The published data contains personalized information, which may be used for analysis converting it to useful information. In this paper, Quasi identifier (QI) data publishing with data preservation through the $K$-anonymization process is proposed. Moreover, the risks such as the temporal attack in the previous release of re-identifying QI information are evaluated using the $K$-anonymity model. The development of independent and ensemble classifiers for finding efficient QI’s to avoid temporal attacks is the major objective of this paper. Therefore, the classifiers like Naïve Bayes, Support Vector Machine, and Multilayer Perceptron are used as base classifiers. An ensemble model based on these base classifiers is also used. The experimental results demonstrate that, the proposed classification approach is an effective K-anonymity tool for the enhancement of sequential release.

The metal–semiconductor (MES)-based through silicon vias (TSV) has provided attractive solutions over conventional metal–insulator–semiconductor (MIS) TSVs in recent three-dimensional (3D) integration. This paper aims a comprehensive performance analysis of MIS and MES structures considering different TSV shapes such as cylindrical, tapered, annular, and square. At 32nm technology, a CMOS-based coupled driver-via-load (DVL) setup is introduced wherein each via is represented an equivalent RLGC model of MIS- and MES-based TSV shapes. The proposed electrical model accurately considers the impact of micro bump and inter-metal dielectric (IMD) effects at 32nm technology as per the fabrication house. A 3D electromagnetic (EM) structural wave simulation is performed to validate the RLGC model parameters of different TSV structures for an operating frequency of up to 20GHz. The proposed DVL setup is used to analyze the propagation delay, power dissipation, and dynamic crosstalk for different MIS- and MES-based TSV shapes. A significant improvement in the cross-coupling behavior can be obtained using the MES-based tapered TSV compared to the other MIS structures. Additionally, the power delay product (PDP) of the tapered MES is reduced by 92.4% compared to the conventional MIS-based cylindrical TSV.

This paper introduces a new premium multilevel inverter (MLI) topology with cascaded H-Bridge and series-parallel connected switches to synthesize the fundamental sine wave with various levels of voltage. The component count is decreased by reducing the number of power switching devices, optoisolators, voltage gate drivers, snubber and filter circuits. The combination of two power switches and a separated DC (SDC) source is called an SDC module. Five SDC modules are required for a 63-level MLI and six SDC modules are required for a 127-level MLI. In this paper, both a 63-level and a 127-level filter-less single-phase MLIs are deliberated. The switches are controlled by employing a newer pulse width modulation (PWM) technique called periodic reduced digital carrier level shift PWM (PRDCLSPWM). As the number of levels increases to a greater extent, the total harmonic distortion diminishes without the need of filter circuit and the performance level also increases. Comparative analysis of proposed 63-level and 127-level MLIs topology with the conventional and modern topologies has been presented in terms of power switches, gate driver circuit requirement, DC voltage sources and THD limits. PRDCLSPWM scheme is derived and analyzed for the proposed 63-level and 127-level MLIs to eliminate low-order and high-order harmonics. Moreover, the performance of the proposed modulation scheme is compared with the most commonly used schemes. The modeling and simulation are done with MATLAB/SIMULINK 2016a.

Coverage-Based Fault Localization (CBFL) techniques are based on the conjecture that the program elements executed by more failed test cases and less passed test cases have more chance to be faulty. Coincidental Correct (CC) test case is one of the negative impacts on CBFL, for the reason that the CC test cases execute the faulty element but not propagate the faulty status to the final output. To alleviate the negative impact of CC test cases, in this paper, we propose a cluster-based technique to identify CC test cases from the passed test suite. To evaluate the effectiveness of our method, we conduct empirical studies on 102 versions from six programs. The experimental results show that, when using our method, it can accurately recognize CC test cases, where the precision and recall rate are both higher than 85%. A further study shows that, after removing identified CC test cases, the fault localization accuracy of SBFL can be improved apparently.

In this paper, the method for the design automation of a narrow band-pass amplifier, and hence the amplifier tuned oscillator is discussed. A fixator approach is utilized in this method to design the narrow band-pass amplifiers and a reference circuit is required for this process. The fixator–norator pair helps to generate an extra sub-circuit, generally the feedback network; the addition of this sub-circuit in the actual amplifier circuit will modify the frequency response of the amplifier. The amplifier now behaves like an active narrow band-pass filter, which exactly follows the frequency response of the model circuit. This can be turned into an oscillator by providing positive feedback. Such a circuit possesses independent frequency and amplitude control. Hence, the re-designed circuit can be employed as an active filter or an oscillator at the selected center frequency. In addition to the technical merits, the proposed method has pedagogical importance. Few case studies are worked out in this paper to demonstrate the method.

Traditional filters usually have low Q and gain values and it is difficult to adjust their center frequencies. Moreover, it is very complicated to analyze their transmission charateristics through conventional methods. Therefore, in this paper, a tunable differential N-path bandpass filter that uses a new adjoint network method to analyze the transmission characteristics of the differential N-path structure is proposed. The filter circuit adopts a novel circuit structure consisting of two differential N-path structures, two transconductance amplifiers and an off-chip transformer. The differential structure eliminates even harmonics, the transconductance amplifier increases the circuit gain and the off-chip transformer acts as a balun, improving the filter’s Q value and achieving impedance matching. Unlike the traditional switching capacitance method used for analyzing the differential circuit structure, the method proposed in this paper does not involve complicated calculus operations. In fact, the method greatly simplifies these complex operations, and the transmission function of the circuit can be obtained through simple algebraic operations. The proposed filter was designed using TSMC 180nm CMOS process. Simulation results for a differential four-path bandpass filter formed under 1.2V supply voltage show that the gain of the filter is greater than 8.5 dB, the center frequency can be adjusted from 0.1GHz to 1GHz, the in-band insertion loss S11 is greater than 10 dB, the out-of-band IIP3 is greater than 10 dBm, the out-of-band rejection is 28 dB and the noise figure is less than 2.2 dB at $f_s=300$MHz.

Wireless sensor networks have fascinating applications that help mankind to get connected with the physical world. Since the last decade, wireless sensor networks are been researched as physical infrastructure of Internet of things technology. For such accomplishment, wireless sensor networks need to be scalable and self-organizing. As sensor nodes are battery driven, limited lifetime is the prime constraint. Clustering methods are popularly used to prolong the network lifetime, but cluster leader selection algorithms majorly affect total energy consumption of the network. This is because cluster leaders utilize more energy than other nodes. For scalable networks, selecting appropriate cluster leaders is a great challenge. In this research work, a distributed cluster leader selection algorithm is proposed to prolong the network lifetime. Real-time network parameters are used instead of random variables or constants in the formulation of cluster leader selection criteria. Due to this, minimal but sufficient number of cluster leaders are selected. This reduces number of transmissions toward the sink and significantly minimizes overall energy consumption. The simulation results indicate that the proposed algorithm enhances network lifetime efficaciously for varying node density and coverage area. Thus, the proposed algorithm can be suitably used for Internet of things applications.