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Multi-Rider Optimization-Based Neural Network for Fault Isolation in Analog Circuits

D. Binu

https://orcid.org/0000-0002-1649-5541

Department of Electronics and Communication Engineering, R V College of Engineering, VTU University, India

E-mail Address: altimatebinu@gmail.com

Corresponding author.

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B. S. Kariyappa

Department of Electronics and Communication Engineering, R V College of Engineering, VTU University, India

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https://doi.org/10.1142/S0218126621500481Cited by:1 (Source: Crossref)

Abstract

Fault isolation in electronic circuits is a trending area of interest as analog circuits find valuable application in industry. The failures in circuit systems cause severe issues in the normal functioning of the system that insists on the need for an automatic method of fault isolation in analog circuits. Literature conveys the issues associated with the fault isolation and hence, to address the severity of the faults, a novel model is proposed to isolate the fault causing component in the circuit. The proposed Multi-Rider Optimization-based Neural Network (M-RideNN) isolates the faulty part of the circuit from the fault-free areas such that the fault diagnosis is structured in an effective way. The fault isolation is progressed as four major steps such as establishing the fault dictionary, signal normalization using Linear Predictive Coding (LPC), effective dimensional reduction methodology using Probabilistic Principal Component Analysis (PPCA), and fault isolation using the proposed M-RideNN classifier. Finally, the experimentation using three circuits, namely Triangular Wave Generator (TWG), Bipolar Transistor Amplifier (BTA), differentiator (DIF), and an application circuit, Solar Power Converter (SPC), proves that the proposed M-RideNN classifier offers better classification accuracy of 93.18% with a minimum Mean Square Error (MSE) of 0.0682.

This paper was recommended by Regional Editor Piero Malcovati.

Keywords:

References

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