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This paper reviews causes of and trends in MOS transistor mismatch, and assesses the implications for analog circuit design in the nanometer régime. The current understanding of MOS transistor mismatch is reviewed. In most cases, transistor mismatch is dominated by threshold voltage mismatch. Although, there is strong evidence that V_T matching is improving as CMOS technology evolves, these improvements are countered by reductions in power supply that also accompany process scaling. In fact, the power consumption of analog circuits based on current design styles will increase with scaling to finer processes. It has long been known that thermal noise causes the power consumption of analog circuits to increase with scaling. However, unlike the case with thermal noise, new circuit techniques can break the accuracy-power constraints related to mismatch. These techniques are based on analog circuit redundancy, and take advantage of the tremendous transistor density offered by nanometer CMOS. This paper is primarily concerned with comparators, and in particular, with the use of comparators in flash ADCs; however, the analysis is also applicable to other circuits and applications.

This paper presents novel CMOS realizations of the operational floating conveyor (OFC) based on novel block diagrams. It also introduces novel applications based on one of the proposed OFC realizations. The proposed OFC realization provides a wide bandwidth and a large gain bandwidth product. Hence, it exhibits wide bandwidth at higher gains. All the circuits in this paper are designed following a fair comparison criterion. The supply voltages are ±1.5 V. The reference DC current source I_B is taken as 50 μA. The CMOS model for all circuits is identical. The transistor model is 0.5 μm CMOS process provided by MOSIS (AGILENT).

The analog-integrated circuits industry is exerting increasing pressure to shorten the analog circuit design time. This pressure is put primarily on the analog circuit designers that in turn demand automated circuit design tools evermore vigorously. Such tools already exist in the form of circuit optimization software packages but they all suffer a common ailment — slow convergence. Even taking into account the increasing computational power of modern computers the convergence times of such optimization tools can range from a few days to even weeks. Different authors have tried diverse approaches for speeding up the convergence with varying success. In this paper authors propose a combined optimization algorithm that attempts to improve the speed of convergence by exploiting the positive properties of the underlying optimization methods. The proposed algorithm is tested on a number of test cases and the convergence results are discussed.

This paper presents two novel Floating Current Source (FCS)-based CMOS negative second generation current conveyor (CCII-) realizations suitable for very large scale implementation. The proposed realizations provide high voltage and current tracking accuracy, as well as large voltage and current transfer bandwidths. Simulation results show that the first proposed wide-band CCII- bandwidth is about 972 MHz. Targeting low-power dissipation, a second low-power version of the wide-band CCII- is proposed at the expense of lower bandwidth and accuracy. The proposed CCII- realizations are layout-friendly because they can be easily fabricated in a systematic modular layout fashion. In addition, a fair comparison is held between the proposed realizations and the only FCS-based CCII- realizations in the literature to show the strength of the proposed circuits. The proposed two CCII- realizations show excellent immunity to process variations and transistor mismatch. In addition, they are insensitive to the temperature variations. Finally, two common CCII- applications are presented.

In this paper, four baseband chain architectures used in multistandard (UMTS–WLAN) reconfigurable receivers will be introduced, simulated and, compared. The architectures are realized using 0.25 μm CMOS technology operating with 1.2 V supply voltage. The baseband chain consists of three stages: the first and the last stage are programmable gain amplifiers and the intermediate stage is an active Gm-RC LPF filter. The proposed architectures are compared in terms of DC-gain, noise, linearity, SFDR, and power consumption. The best receiver architecture is then derived based on system level analysis and based on a defined figure-of-merit. The best baseband chain bandwidth is controlled by the active G_m-RC filter with a value 2.2 MHz for UMTS and 11 MHz for WLAN. The baseband gain can be programmed in the range of -6÷68 dB, while the input-referred noise density is less 20 nV/√Hz for UMTS and 25 μV/√Hz for WLAN.

In a recent paper published in this journal, Soliman presented the methods of transformation of grounded inductors to floating inductors using operational floating amplifiers and floating second generation current conveyors. The purpose of this note is to bring on record the present author's earlier works on the same topic published about 24 years back which are closely related to the work reported in Soliman's paper but have not been cited therein.

This paper presents an approach to the design of a high-precision CMOS voltage reference. The proposed circuit is designed for TSMC 0.35 μm standard CMOS process. We design the first-order temperature compensation bandgap voltage reference circuit. The proposed post-simulated circuit delivers an output voltage of 0.596 V and achieves the reported temperature coefficient (TC) of 3.96 ppm/°C within the temperature range from -60°C to 130°C when the supply voltage is 1.8 V. When simulated in a smaller temperature range from -40°C to 80°C, the circuit achieves the lowest reported TC of 2.09 ppm/°C. The reference current is 16.586 μA. This circuit provides good performances in a wide range of temperature with very small TC.

A new cascadable voltage-input, current-output first-order all-pass filter and its applications in second-order filter and oscillator are presented. The proposed circuit employs a single active element namely extra-X current-controlled current conveyor (EX-CCCII) and only a single grounded capacitor. The circuit exhibits high input and high output impedances, so that the filter can be cascaded without additional buffers. The pole frequency is electronically tunable and the circuit requires no component matching constraints. Effects of nonidealities and parasitics are also discussed. As applications, a second-order transadmittance (TA)-mode all-pass filter and a quadrature oscillator are also realized using the proposed voltage-input, current-output first-order all-pass filter. These examples validate easy cascading feature of the proposed circuit. The validity of the proposed circuit is verified through PSPICE simulations using 0.25$\mu$m parameters with a supply voltage of $\pm 1.25$V.

This paper presents a novel method for the design of analog integrated circuit, making use of fixator–norator pairs for the performance design and biasing design. Fixators are the distinctive tools for setting a critical design parameter at a desired value whereas the pairing norator renders these critical parameters into adequate supporting components, mainly resistors. For analog ICs, active loads and current mirrors serve as supporting components. Hence, the use of fixator–norator pairs may abbreviate as defining the dynamic and static resistance of active loads and current mirrors that should be affirmative with a given design. The proposed methodology is illustrated by the use of a common emitter amplifier, a BJT differential amplifier, a MOS operational amplifier and a three-stage CMOS operational amplifier.

Smart image sensors with low data rate output are well fitted for security and surveillance tasks, since at lower data rates, power consumption is reduced and the image sensor can be operated with limited energy resources such as solar panels. In this paper, a new data transfer scheme is presented to reduce the data rate of the pixels which have undergone value change. Although different pixel difference detecting architectures have been previously reported but it is shown that the given method is more effective in terms of power dissipation and data transfer rate reduction. The proposed architecture is evaluated as a $100\times 160$-pixel sensor in a standard CMOS technology and comparison with other data transfer approaches is performed in the same process and configuration.

Feedback is an integral part of many analog circuits. This paper presents a method for the design of feedback networks for analog amplifiers based on Fixator–Norator Pair (FNP). The design process for required transfer function includes inserting proper FNPs to the equivalent small signal model of the target circuit, with norators lying along the feedback path, and helps to design the feedback network components. Care must be taken to ensure that the added feedback should not alter the original DC biasing of the circuit. A number of examples are worked out in this paper using the proposed method and the results are verified. The FNP approach gives a one-step solution for the design problems which otherwise require tedious analysis and calculations. Although the scope of this paper is limited to design of feedback for amplifiers, a skillful designer can extend the proposed method to other areas of analog circuits.

In this work, novel swarm optimization algorithm based on the Artificial Bee Colony (ABC) algorithm called Enhanced Artificial Bee Colony (EABC) algorithm is proposed for the design and optimization of the analog CMOS circuits. The new search strategies adopted improve overall performance of the proposed algorithm. The performance of EABC algorithm is compared with other competitive algorithms such as ABC, GABC (G-best Artificial Bee Colony Algorithm) and MABC (Modified Artificial Bee Colony Algorithm) by designing three CMOS circuits; Two-stage operational amplifier, low-voltage bulk driven OTA and second generation low-voltage current conveyor in 0.13 $\mu$m and 0.09$\mu$m CMOS technologies. The obtained results clearly indicate that the performance of EABC algorithm is better than other mentioned algorithms and it can be an effective approach for the automatic design of the analog CMOS circuits.

This paper presents an electronically tunable current-mode first-order universal filter. The proposed circuit employs only a single Extra-X Current-Controlled Conveyor (EX-CCCII) and a single grounded capacitor, which is suitable for IC implementation. The circuit can realize three current transfer functions simultaneously, namely low-pass, high-pass and all-pass. The proposed circuit exhibits low-input and high-output impedance, which is suitable for cascading. The pole frequency of the filter can be electronically tuned, by varying the bias current of EX-CCCII. The nonidealities and parasitic effects on the circuit performance are investigated in detail. Also, the Monte Carlo analysis is done to show the effect of active and passive element mismatches on the pole frequency. An eight-phase current-mode sinusoidal oscillator and current-mode second-order filter are further realized using the proposed circuit. The functionality of the proposed circuits is verified through PSPICE simulations, using 0.25-$\mu$m TSMC CMOS technology parameters.

Fault isolation in electronic circuits is a trending area of interest as analog circuits find valuable application in industry. The failures in circuit systems cause severe issues in the normal functioning of the system that insists on the need for an automatic method of fault isolation in analog circuits. Literature conveys the issues associated with the fault isolation and hence, to address the severity of the faults, a novel model is proposed to isolate the fault causing component in the circuit. The proposed Multi-Rider Optimization-based Neural Network (M-RideNN) isolates the faulty part of the circuit from the fault-free areas such that the fault diagnosis is structured in an effective way. The fault isolation is progressed as four major steps such as establishing the fault dictionary, signal normalization using Linear Predictive Coding (LPC), effective dimensional reduction methodology using Probabilistic Principal Component Analysis (PPCA), and fault isolation using the proposed M-RideNN classifier. Finally, the experimentation using three circuits, namely Triangular Wave Generator (TWG), Bipolar Transistor Amplifier (BTA), differentiator (DIF), and an application circuit, Solar Power Converter (SPC), proves that the proposed M-RideNN classifier offers better classification accuracy of 93.18% with a minimum Mean Square Error (MSE) of 0.0682.

In this paper, the method for the design automation of a narrow band-pass amplifier, and hence the amplifier tuned oscillator is discussed. A fixator approach is utilized in this method to design the narrow band-pass amplifiers and a reference circuit is required for this process. The fixator–norator pair helps to generate an extra sub-circuit, generally the feedback network; the addition of this sub-circuit in the actual amplifier circuit will modify the frequency response of the amplifier. The amplifier now behaves like an active narrow band-pass filter, which exactly follows the frequency response of the model circuit. This can be turned into an oscillator by providing positive feedback. Such a circuit possesses independent frequency and amplitude control. Hence, the re-designed circuit can be employed as an active filter or an oscillator at the selected center frequency. In addition to the technical merits, the proposed method has pedagogical importance. Few case studies are worked out in this paper to demonstrate the method.

This paper introduces a charge-controlled memristor based on the classical Chuas circuit. It also designs a novel four-dimensional chaotic system and investigates its complex dynamics, including phase portrait, Lyapunov exponent spectrum, bifurcation diagram, equilibrium point, dissipation and stability. The system appears as single-wing, double-wings chaotic attractors and the Lyapunov exponent spectrum of the system is symmetric with respect to the initial value. In addition, symmetric and asymmetric coexisting attractors are generated by changing the initial value and parameters. The findings indicate that the circuit system is equipped with excellent multi-stability. Finally, the circuit is implemented in Field Programmable Gate Array (FPGA) and analog circuits.

This work describes voltage-mode (VM), current-mode (CM) PID controllers and an electrically controllable floating inductance (FI) simulator circuit. Only a single current-controlled current backward transconductance amplifier (CC-CBTA) and a grounded capacitor are used in the proposed FI simulator circuit. One CBTA, one CC-CBTA, two capacitors and one resistor are used in the proposed PID controllers. All of the proposed circuits have appropriate input and output impedance values, allowing them to be utilized in cascade connections without requiring a buffer circuit. There is also no matching constraint between the active and passive values of the proposed circuit. The SPICE software environment and experimental results were used to validate theoretical derivations and associated outcomes. The layout of the CC-CBTA has been built, and the post-layout simulations are carried out using the netlist extracted from the layout. Comparisons were made with similar circuits found in the professional literature.

To identify whether the circuit under test is fault-free or faulty, fault diagnosis is conducted in an analog circuit. However, in the case of fault detection (FD) techniques, the size of FD is the main challenge in testing, especially for complex analog circuits. Hence to reduce the size of FD, specific test nodes are chosen to perform fault diagnosis from the available accessible test nodes. Specific test nodes are selected based on the faults classification efficiency of fault diagnosis. Therefore, this paper proposes an approach for single and multiple soft fault diagnosis using minimum test nodes in analog electronic circuits. The proposed double deep Q-learning-based hybrid Simulated annealing–Tabu search (DDQN-Hybrid SATS) technique determines minimum test nodes with the utilization of distance metric for fault classification. The DDQN-Hybrid SATS technique is used to identify minimum nodes for testing. In this, the double deep Q learning network (DDQN) ensures better reliability and faster convergence in learning but suffers from catastrophic forgetting issues. To prevent such issues, the DDQN approach is optimized using a hybrid SATS algorithm. The hybrid optimization of simulated annealing (SA) and Tabu search (TS) coalesce the advantages of individual optimization procedures to provide the optimum solution in a fast and effective way. The results for a fourth-order low pass filter are presented (i.e., first CUT) and an eight-bit digital to analog converter (i.e., second CUT). Moreover, the simulation experiment reveals that the proposed DDQN-Hybrid SATS technique achieves greater overall fault classification accuracy of about 96.25% than other compared techniques with minimum computation time.

This paper presents the structure and operational principles of high-frequency electronically controllable sinusoidal oscillators employing current-feedback operational amplifiers (CFOAs) with externally accessible compensation node $z$ as active components. The resonant circuits in the oscillators are connected to the terminal $z$, and for them in the selective network varactor diodes or varicaps as the variable capacitances are utilized, which are controlled by external DC voltage. Based on an analysis of the proposed circuit configurations, analytical expressions for the characteristic equation in a steady-state mode of operation and formulas for the basic electrical parameters have been obtained. In order to verify the functionality of the proposed electronic circuits and the effectiveness of the derived analytical expressions, an experimental and simulation study of sample electronic circuits with commercially available integrated circuit CFOAs AD844 in the frequency range up to about 10MHz is performed. The obtained results for the studied electronic circuits confirm the theoretical studies and hypotheses, and the comparative analysis shows that the maximum value for the relative error does not exceed 10%, which is acceptable considering the tolerances of the technological parameters of the used passive and active elements.

In this paper we discuss the possible use of chaotic signals for testing Analog-to-Digital Converters (ADCs), with particular reference to the well-known Code Density Test (CDT, also called Histogram Test). In detail, we discuss the implementation of a chaos-based discrete-time noise generator circuit, providing the theoretical analysis of its statistical characterization. The implementation of the chaos-based device is discussed with reference to a generic hardware architecture, taking into account the nonidealities introduced by the presence of noise and the variability of the circuit parameters. Based on this device, we propose a method for generating noisy samples that are distributed, over a target subinterval of the circuit output range, according to a probability density function (pdf) that can be made arbitrarily close to the ideal uniform pdf, in exchange for an acceptable reduction of the uniform-distributed samples generation rate. Theoretical results, also supported by two experiments, confirm the reliability of the proposed solution, showing that chaotic systems can represent an alternative with respect to traditional methods for the generation of signals to be used in the Code Density Test of ADCs.