Journal of Circuits, Systems and Computers

Widespread growth of multimedia content distribution can increase the cost and time of the content distribution. The multimedia services are stored by the service provider and the user is provided based on their demand. Basically, the network user number increases quickly, and the response time for huge numbers of users also increases rapidly. Therefore, the need of service cannot be reached. Initially, we solicited notable extraction technique to collect the interest features of user. The adjacent region and similar service interests of users are divided into service user and nonservice user. Therefore, the coherent utility value is suggested to the user evaluation procedure, so the combination of different users experience character is needed to calculate the integrated utility value. Hence, the users experience characteristics are derived by presentation of physical user, behavior of selfish user and character of the user. Consequently, we minimized the content distribution cost and time with crossover-based sine cosine algorithm (CSCA). The proposed CSCA was established for the selection of user service number. The experimental results of proposed method can decrease the multimedia user cost and improve the performance of multimedia content.

In feature-level image fusion, deep learning technology, particularly convolutional sparse representation (SR) theory, has emerged as a new topic over the past three years. This paper proposes an effective image fusion method based on convolution SR, namely, convolutional sparsity-based morphological component analysis and guided filter (CS-MCA-GF). The guided filter operator and choose-max coefficient fusion scheme introduced in this method can effectively eliminate the artifacts generated by the morphological components in the linear fusion, and maintain the pixel saliency of the source images. Experiments show that the proposed method can achieve an excellent performance in multi-modal image fusion, which includes medical image fusion.

The numerically controlled oscillator is often supposed to operate after interpolation in a conventional digital up converter, but such a converter works at quite high frequencies and consumes more power. In this paper, a type of low power structure digital up converter is proposed which carries out mixing and interpolating gradually, where the numerically controlled oscillator and the interpolation filter can both work at a lower frequency. Low power structure can move signal to any position within the whole Nyquist Band. Furthermore, the interpolation filter adopts a half-band filter with the structure of two parallel branches, which combines the functions of stuffing zero, filtering and modulation, and makes programmable modulation by exchanging input paths. A simulation is carried out on the Xilinx KC705 development kit, which indicates that its maximum work frequency of the low power structure reaches 392MHz while its power consumption reduces by 33.3% compared to the conventional structure.

This paper presents Deep Rain Streaks Removal Convolutional Neural Network (Derain SRCNN) based post-processing optimization algorithm for High-Efficiency Video Coder (HEVC). Earlier, the CNN-based denoising optimization algorithm faced overfitting issues and large convergence time when training the CNN for rain streaks affected High Definition (HD) video sequences. To address these problems, Deep rain streaks removal CNN-based post-processing block is introduced in HEVC encoder. Derain SRCNN architecture consists of a parallel two residual block layer and Dual Channel Rectification Linear Unit (DCReLU) activation function with various sizes of the convolutional layer. By reducing the validate error and training the error of CNN, the overfitting issue is solved. Also, convergence time is reduced using proper learning rate and kernel weight of optimization algorithm. The proposed network provides a higher bit rate reduction and higher convergence speed for corrupted high-definition video sequences. The experiment result shows that proposed DerainSRCNN-based post-processing filtering method achieves 6.8% and 4.1% -bit rate reduction for random access (RA) and low delay $P$ frame (LDP) configuration, respectively.

The two-dimensional Gaussian smoothing filter (2D-GSF) is one of the most useful techniques in image processing. Since the 2D-GSF requires high computational resources, its efficient design and implementation are critical in real-time processing purposes. Approximate computing is a new method that can be used to increase the performance of 2D Gaussian filter design with low computing overhead on field-programmable gate arrays (FPGAs). This study aims to provide a low-latency Gaussian filter architecture on FPGA such that it can be used in real-time processing applications. In this regard, accurate and approximate carry-save adders (CSAs) have been used in adder tree-based Gaussian filters. In our proposed method, we use two approximation steps: in the first step, we use an approximation structure named Speed–Power–Area–Accuracy for Gaussian filter design and in the second stage, we use approximate CSAs to convert adder-tree structures that are used in Gaussian filter, and as a result, we have significantly reduced the delay. The results of simulation and implementation show that the latency has reduced in a 3$\times$ 3 2D-GSF architecture up to 22% using proposed accurate CSAs and 45% using proposed approximate CSAs, compared to existing Gaussian filters with an adder tree structure.

Pedestrian recognition has achieved the state-of-the-art performance due to the progress of recent convolutional neural network (CNN). However, mainstream CNN models are too complicated to emerging Computing-In-Memory (CIM) architectures for hardware implementation, because enormous parameters and massive intermediate processing results may incur severe “memory bottleneck”. This paper proposed a design methodology of Parameter Substitution with Nodes Compensation (PSNC) to significantly reduce parameters of CNN model without inference accuracy degradation. Based on the PSNC methodology, an ultra-lightweight convolutional neural network (UL-CNN) was designed. The UL-CNN model is a specially optimized convolutional neural network aiming at a flash-based CIM architecture (Conv-Flash) and to apply for recognizing person. The implementation result of running UL-CNN on Conv-Flash shows that the inference accuracy is up to 94.7%. Compared to LeNet-5, on the premise of the similar operations and accuracy, the amounts of UL-CNN’s parameters are less than 37% of LeNet-5 at the same dataset benchmark. Such parameter reduction can dramatically speed up the training process and economize on-chip storage overhead, as well as save the power consumption of the memory access. With the aid of UL-CNN, the Conv-Flash architecture can provide the best energy efficiency compared to other platforms (CPU, GPU, FPGA, etc.), which consumes only 2.2 × 105J to complete pedestrian recognition for one frame.

This paper offers a novel, low-power, hardware-efficient, yet high-frequency architecture for a power spectral density (PSD) estimator, based on the Bartlett method, for low-power biomedical applications. The Bartlett method is a nonparametric method for PSD estimation. The proposed architecture operates based on a modified multiplierless 64-point optimized radix-2² single-path delay feedback (R2²SDF) FFT processor. To obtain the final result, it also uses modified safe-scaling in a way that removes the need to use several extra hardware units. It takes advantage of combined coefficient selection and shift-and-add implementation (CCSSI) for computing twiddle factors which is a new algorithm based on digital computer coordinate rotation (CORDIC) for generating trigonometric values. The proposed method has the capability of operating on short word lengths (WLs). Artix-7 is the FPGA used in this research and Verilog is the language used for hardware design. For 8-bit WL and 244-mW power, a frequency of 286 MHz has been achieved. Several vital signals are used for performance comparison of the proposed technique with state-of-the-art designs.

A regulated power supply with ultra-low-power consumption, high current efficiency, line, load and thermal stability is an essential part of any high precision electronic system with stringent power budget such as biomedical sensors or military surveillance systems. In this paper, we propose an ultra-low-power, MOSFET only, voltage reference to regulator convertor, proficient to work below 1 V with reduced power consumption. The proposed idea incorporates the provision to integrate any voltage reference module to a comparator-based circuit so as to transform it to a voltage regulator having similar temperature coefficient (TC) and line regulation as that of the interfaced voltage reference. It is also able to produce a reliable output accounting to load fluctuations. The circuit is simulated in 0.18$\mu$m CMOS technology using Cadence Virtuoso simulation suit. The complete circuit was found to draw a quiescent current of 319.9 pA with a notable current efficiency of 99.99997% at 27^∘C on driving a load of 1mA along with a Power Supply Rejection Ratio (PSRR) of $-117$dB additional to that of the reference. The proposed circuit will occupy an area of 0.00064mm² and offer a TC as low as 1.7077 ppm/^∘C. The whole MOS approach facilitates a reduction in die area and process simplicity.

Since Deep Neural Networks (DNNs) have been more and more widely used in safety-critical Intelligent System (IS) applications, the robustness of DNNs becomes a great concern in IS design. Due to the vulnerability of DNN models, adversarial examples generated by malicious attacks may result in disasters. Although there are plenty of defense methods for these adversarial attacks, existing methods can only resist special adversarial attacks. Meanwhile, the accuracy of existing methods degrades dramatically when they process nature examples. To address this problem, we propose an effective Cooperative Defensive Architecture (CDA) that can enhance the robustness of IS devices by integrating heterogeneous base classifiers. Because of the parallel mechanism in ensemble learning, the compressed heterogeneous base classifiers do not increase the prediction time on device. Comprehensive experimental results show that the modified DNNs by our approach cannot only resist adversarial examples more effectively than original model, but also achieve a high accuracy when they process nature examples.

Nowadays, lightweight cryptography attracts academicians, scientists and researchers to concentrate on its requisite with the increasing usage of low resource devices. In this paper, a new lightweight image encryption scheme is proposed using the Lorenz 3D super chaotic map. This encryption scheme is an addition–rotation–XOR block cipher designed for its supremacy, efficacy and speed execution. In this addition–rotation–XOR cipher, the equation for Lorenz 3D chaotic map is iteratively solved to generate double valued signals in a speedy manner using the Runge–Kutta and Euler methods. The addition, rotation and diffusion sequences are generated from the double valued signals, and the source pixels of the 8-bit plain test images are manipulated with the addition, rotation and diffusion of the bytes. Finally, the cipher images are constructed from the manipulated pixels and evaluated with various statistical as well as randomness tests. The results from various tests prove that the proposed chaotic addition–rotation–XOR block image cipher is efficient in terms of randomness and speed.

Sea-land segmentation based on edge detection is commonly utilized in ship detection, coastline extraction, and satellite system applications due to its high accuracy and rapid speed. Pixel-level distribution statistics do not currently satisfy the requirements for high-resolution, large-scale remote sensing image processing. To address the above problem, in this paper, we propose a high-throughput hardware architecture for sea-land segmentation based on multi-dimensional parallel characteristics. The proposed architecture is well suited to wide remote sensing images. Efficient multi-dimensional block level statistics allow for relatively infrequent pixel-level memory access; a boundary block tracking process replaces the whole-image scanning process, markedly enhancing efficiency. The tracking efficiency is further improved by a convenient two-step scanning strategy that feeds back the path state in a timely manner for a large number of blocks in the same direction appearing in the algorithm. The proposed architecture was deployed on Xilinx Virtex k7-410t to find that its practical processing time for a $32,768\times 1,024$ remote sensing image is only about 0.4s. The peak performance is 1.625gbps, which is higher than other FPGA implementations of segmentation algorithms. The proposed structure is highly competitive in processing wide remote sensing images.

In this paper, we investigate the direction of arrival (DOA) estimation problem of noncircular signals for coprime linear array (CLA). From the perspective of the CLA as extracted from a filled uniform linear array (ULA), a noncircular root-MUSIC algorithm is proposed to estimate the DOA which can avoid the spectral peak search and lower the computational complexity. Due to the noncircular characteristic, the proposed algorithm enables to resolve more sources than sensors. Meanwhile, the proposed algorithm has better angle estimation performance than some conventional DOA estimation algorithms. Numerical simulation results illustrate the performance of the proposed method.

A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28$\mu$W power consumption in a standard 0.18$\mu$m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17ppm/^∘C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that $\sigma$/$\mu$ of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.

Based on the ElectroEncephaloGraphy (EEG) signals obtained by noninvasive methods, Brain–Computer Interface (BCI) technologies provide real-time communication of individuals within the cyber-physical systems. However, this research area still needs low-cost solutions to become a research topic widely all around the world. In this paper, a low cost and productive BCI equipment was developed to assist daily living activities for disabled people. The control application of an integrated approach aims to open and close a door equipped with an EEG-based lock system using eye blink signals is developed. The proposed easy-to-use, portable BCI system includes cost-effective hardware/software components, modular and flexible configuration features and Bluetooth-enabled real-time data processing units. The developed BCI hardware is based on Texas Instruments ADS1299 AFE ADC, which features high flexibly in configuring of measure of various biopotentials from the human body using designed active/passive dry electrodes. Besides it is equipped with a built-in real-time data storage unit and accelerometer to make an online diagnosis, and data fusion at the interested signal investigation. Furthermore, desktop software has been implemented in the QT SDK environment, which can integrate remote BCI hardware during configuration. Experimental results of the designed system were compared with the results of the commercial-grade counterpart.

Recently, deep trackers based on the siamese networking are enjoying increasing popularity in the tracking community. Generally, those trackers learn a high-level semantic embedding space for feature representation but lose low-level fine-grained details. Meanwhile, the learned high-level semantic features are not updated during online tracking, which results in tracking drift in presence of target appearance variation and similar distractors. In this paper, we present a novel end-to-end trainable Convolutional Neural Network (CNN) based on the siamese network for distractor-aware tracking. It enhances target appearance representation in both the offline training stage and online tracking stage. In the offline training stage, this network learns both the low-level fine-grained details and high-level coarse-grained semantics simultaneously in a multi-task learning framework. The low-level features with better resolution are complementary to semantic features and able to distinguish the foreground target from background distractors. In the online stage, the learned low-level features are fed into a correlation filter layer and updated in an interpolated manner to encode target appearance variation adaptively. The learned high-level features are fed into a cross-correlation layer without online update. Therefore, the proposed tracker benefits from both the adaptability of the fine-grained correlation filter and the generalization capability of the semantic embedding. Extensive experiments are conducted on the public OTB100 and UAV123 benchmark datasets. Our tracker achieves state-of-the-art performance while running with a real-time frame-rate.

Accurate ramp signal, with low power dissipation, is highly demanded, for applications like counter ADC. This paper presents a novel low power ramp generator circuit with a negative feedback loop for compensation of the variations in process, voltage, and temperature (PVT). While using an opamp for PVT compensation has been essential in the previous ramp generator structures, the proposed ramp generator is opamp-less. Derived equations of the proposed ramp generator circuit show that PVT compensation structure works effectively. In addition, the circuit design and simulations were done in TSMC 0.18$\mu$m CMOS technology. Corner analysis shows that integral non-linearity (INL) of the ramp signal is about 3.7mV, for a wide temperature range, while the power dissipation of the circuit is about 1.16$\mu$W.

In order to improve the slew rate of rail-to-rail operational amplifiers, this paper presents a novel slew boosting circuit. Two slew-boosting unit circuits are proposed to provide large compensation current by directly detecting the differential level change at the input terminals of the amplifier. Accordingly, the slewing performance is dynamically boosted. In each slew-boosting unit circuit, tunnel diodes are used to replace the conventional MOS transistors as loads. This circuit is designed in 1.0$\mu$m TVS process. Measurement results show that the rail-to-rail operational amplifier achieves a positive slew rate of 164V/$\mu$s and negative slew rate of 185V/$\mu$s.

This paper is formulated keeping in view the need of compact antennas for wireless body area network (WBAN). The designed compact dual-band antenna (20mm $\times$ 22mm $\times$ 3.55mm) radiates at two resonant frequencies in the ultra-wideband (UWB) range. Compactness in the designed antenna is attained by using three different layers of copper and the return loss and gain characteristics are improved by incorporating a G-shape defected ground structure (DGS). The proposed antenna is unidirectional and immune to human contact since it is designed in the UWB range (3.1–10.6GHz) which makes it highly suitable for WBAN applications as its low radiating power is harmless for human tissues. The substrate used for design is RT/duroid with a relative permittivity of 2.2. The antenna exhibits superior frequency domain characteristics with simulated $S_{11}$ of $-$16.39dB for 4.08GHz and $-$21.87dB for 8.18GHz and realized gain of 3.69 and 6.02dB for 4.08 and 8.18GHz, respectively. The measured $S_{11}$ depicts a shift to the lower band for the fabricated antenna with the values of $-$15.36dB for 3.55GHz and $-$21.66dB for 6.218GHz.

This paper approximates the behavior of low-pass Bessel filter in fractional domain using the Interior search algorithm (ISA). A detailed analysis has been done with sensitivity analysis, W-plane stability and absolute percentage error (gain and cut-off frequency) to study the low-pass fractional order filter. The work focuses on the analysis and design of fractional filter with two cases. In the first case, the design and simulation of $(1+\alpha )$ order low-pass Bessel filter has been done using MATLAB for $\alpha$ value ranging from 0.1 to 0.9. SPICE simulation of 1.2, 1.5 and 1.9 order low-pass Bessel filter using fractional order capacitor of order $\alpha$ with Tow–Thomas biquad have been performed. In the second case, low-pass ($\alpha +\beta )$ order Bessel filter has been simulated and designed using MATLAB, where $\alpha$ and $\beta$ are two fractional order elements of a different order. SPICE simulation for different values of $\alpha$ and $\beta$ have been done using two fractional order capacitors of $\alpha$ and $\beta$ order with Tow–Thomas biquad.

The class-imbalance learning is one of the most significant research topics in the data mining and machine learning. Imbalance problem means that one of the classes has much more samples than that of other classes. To deal with the issues of low classification accuracy and high time complexity, this paper proposes an novel imbalance data classification algorithm based on clustering and SVM. The algorithm suggests under-sampling in majority samples based on the distribution characteristics of minority samples. First, specific clusters are detected by cluster analysis on the minority. Second, a cluster boundary strategy is proposed to eliminate the bad influence of noise samples. To structure a balanced dataset for imbalance data, this paper proposes three principles of under-sampling on majority samples according to the characteristic of samples in the cluster. Finally, the optimal classification model from the linear combination of hybrid-kernel SVM is obtained. The experiments based on datasets in UCI and KEEL database show that our algorithm effectively decreases the interference of noise samples. Compared with the SMOTE and Fast-CBUS, the proposed algorithm not only reduces the feature dimension, but also improves the precision of the minor classes under the different labeled sample rates generally.