Journal of Circuits, Systems and Computers

The internal combustion engine plays a very important role in many fields, and when the internal combustion engine fails, if it is not found in time, it may cause continuous damage to the internal combustion engine, and further affect the life of the entire mechanical system. To solve the above problems, this paper proposes fault detection of internal combustion engines based on a random convolutional neural network. The cylinder burst noise signal of the internal combustion engine is decomposed by a stationary wavelet, and the inclusion matrix is composed of partial decomposition coefficients. Using singular value theory, the singular value containing matrix is extracted as the characteristic of cylinder burst noise signal. The singular value is used as the input of a random convolutional neural network to train and identify faults. The AdaBound optimizer was then applied to adapt the learning rate to changes, thereby accelerating the weight update of the model. At the same time, the neurons in the structure are randomly deactivated by dropout technology to prevent complex collaborative responses to the training data, and the diagnosis results of each network model are integrated by Dempster synthesis rules. The experimental results show that the minimum mean square error of 0.00165 is achieved when there are 15 neurons in the hidden layer, and it gradually increases as the number of neurons increases. Therefore, it is determined that there should be 15 neurons in the hidden layer, and the trainLM algorithm is used. The decision factors for training, validation, cross-validation, and overall data are 0.98947, 0.98597, 0.97738, and 0.9801, respectively, all reaching the control accuracy of 0.95, which indicates that the random convolutional neural network proposed has a high accuracy for internal combustion engine fault detection. For the main bearing Y-directional force, as the gap increases, its fluctuation trend strengthens; the main bearing force changes within a small range at first, then increases sharply when the gap reaches 0.2mm, and some main bearings even experience significant impact loads.

The energy-efficient error-tolerant circuits have paved the way for a whole new area in low-power consumption applications with approximate computing. The approximate computing fulfills the trade-off requirement of exact computation and provides efficient performance. In this paper, a novel energy-efficient multiplier has been proposed for image processing applications. In the multiplication process, compressors are used as an important component for the reduction of partial products. Higher-order approximate 5:2 and 6:2 compressors are also designed and simulated in VIVADO using Verilog coding. The proposed higher-order compressors result in less area and low-power consumption in comparison with the existing state-of-the-art technique. These high-performance compressors are used at the multipliers’ reduction stage, resulting in an energy-efficient circuit for error-tolerant applications. All the simulations were carried out in VIVADO considering 8-bit inputs. Multiplication performance shows 37.77 % (8-bit) improvement in terms of power consumption in comparison to the conventional multiplier. The multiplication process has been done on the original, negative, and sharpened images using their masks. The proposed multiplier shows 51.36% (original image), 6.04% (negative image), and 22.44% (sharpened image) PSNR improvement in comparison to state-of-the-art work.

Diverse applications in today’s digital era have a high demand for low-power, faster, and high-performance arithmetic circuits. In a multiplier, the power is the costliest part of carrying out partial products. A compressor type of adder is used for faster operation and has lesser power consumption. In this paper, a low-power, energy-efficient 4:2 compressor design has been presented. The proposed design is based on multi-threshold logic. A capacitive network has been used at the input side instead of resistors for better circuit operations. The CNFET-based network is used to design the same. Powers, delay, PDP, and EDP of the proposed design have been computed. It is observed that with 32nm CNFET technology it shows a maximum improvement in PDP and EDP of 69% and 70%, respectively. Moreover, extensive performance analyses against power supply, channel length, temperature, load, and operating frequency have been presented. Finally, the proposed compressor is applied to design Wallace’s multiplier which shows that it outperforms all other designs considered in this study. This indicates that the proposed compressor is quite useful for low-power VLSI circuits and systems applications.

Quantum-dot cellular automata (QCA) technology is one of the nanotechnologies which attracted a great deal of consideration because of features like the speed of the circuit, low-power utilization and small size. In digital electronics, the comparator plays a vital role, due to its vast area of applications like state machine design, digital testing and fault tolerance, digital control systems, etc. This paper proposes a 4-bit/8-bit/16-bit comparator in QCA technology using the XOR Gate. The proposed method is an efficient method, which has two stages: finding whether the inputs are equal or not in stage 1 and less than or greater than in stage 2 using an XOR gate. The proposed comparator circuits have less area and cost with less delay as compared to the previous works. The proposed energy calculations are carried out with the QCA DesignerE tool, and it is observed that the proposed structures are energy efficient. In addition, the proposed comparators are simulated and synthesized with Vivado design suite 2021.1 and implemented on the Virtex UltraScale VCU129-PP FPGA board.

Convolutional neural networks (CNNs) are becoming increasingly popular for image denoising. U-Nets, a type of CNN architecture, have been shown to be effective for this task. However, the impact of shallow layers on deeper layers decreases as the depth of the network increases. To address this issue, the authors propose a new image denoising method called DGANDU-Net. DGANDU-Net combines the DeblurGAN design with a U-Net architecture. This combination allows DGANDU-Net to effectively remove noise from images while preserving fine details. The authors also propose the use of two loss functions, mean square error (MSE) and perceptual loss, to improve the performance of DGANDU-Net. MSE is used to learn and improve the extracted features, while perceptual loss is used to produce the final denoised image. The authors evaluate the performance of DGANDU-Net on a variety of noise levels and find that it outperforms other state-of-the-art denoising algorithms in terms of both visual quality and two evaluation indices, including peak signal-to-noise ratio (PSNR) and Structural Similarity Index Measure (SSIM). Specifically, for extremely noisy environments with a noise standard deviation of 75, DGANDU-Net achieves an average PSNR of 37.39dB in the test dataset. The authors conclude that DGANDU-Net is a promising new method for image denoising that has the potential to significantly improve the quality of medical images used for diagnosis and treatment.

Over the past decades, organic electronics have attracted wide research attention in transistors. One of the devices is organic field effect transistors (OFET), which brought a great revolution for their excellent mechanical flexibility, lightweight, low-temperature deposition, low manufacturing cost and conformable large coverage area, in contrast to conventional silicon-based transistors. This paper highlights the overview of OFET structure, operation and electrical parameters that affect the performance. The influence of gate dielectric thickness, electrode width and channel length on the behavior of transistors in terms of threshold voltage, current ratio and saturation mobility value has also been discussed. The progress in the development of organic semiconductor materials is also outlined, which helps to resolve the power consumption issue.

Spin Orbit Torque Magnetic Random Access Memory (SOT–)MRAM is gaining interest as it eradicates several limitations posed by its predecessor Spin Transfer Torque (STT-)MRAM, yet inherits all its advantages. This work explores in detail, the suitability of SOT–MRAM implemented caches in different levels of memory hierarchy in comparison to conventional SRAM technology, over several performance parameters like area, energy consumption and execution time for an embedded benchmark suite. Our circuit-level analysis shows that SOT–MRAM outperforms SRAM for caches ($>128$ KB), and only lags in area and read-access energy for smaller caches. A typical 512 KB SOT–MRAM cache improves area by 1%, read/write latency by 33/38%, and leakage by over 99% than that of SRAM memory technology. The architecture-level analysis confirms that on average SOT–MRAM is energy efficient by 74% in L1, 97.2% in L2 and 89.3% in both (i.e., L1 + L2) implementations against SRAM, for a 22nm technology node. We also estimate that SOT–MRAM only solution offers $\sim 68.8$% energy savings and $\sim 79.5$% better EDP than Hybrid (L1-SRAM and L2-SOT) memory hierarchy for multi-core ARM processors.

Data-driven smart investment decisions are important for financial development, which has not received much attention from academia. As a result, this paper resorts to the evolutionary game theory, and proposes a novel multi-agent financial investment decision method. Specifically, an evolutionary game theory-based decision-making approach is formulated as the main model for the research purpose. By considering the strategic choices and adaptability among various entities, a comprehensive analysis of the behavior and decision-making process of entities in the financial market is achieved. This paper combines stock exchanges and financial data providers (Bloomberg and Thomson Reuters) to conduct case studies on this method, verifying its effectiveness and feasibility in practical applications. By comparing traditional financial investment decision-making methods, it can be seen that the proposal has significant advantages in improving investment efficiency, reducing risks, and responding to market volatility. This paper delves into the multi-agent financial investment decision-making method based on the evolutionary game, providing new ideas and methods for academic research and practical applications in the financial field.

The advancement of novel technologies has positioned mobile wireless networks as the central focus of computer technology research. The selection process for the subsequent relay node in message forwarding holds paramount importance and is deemed critical. Drawing inspiration from Social Mobility theory, this paper presents a pioneering node classification model that categorizes all nodes into three distinct types. Furthermore, we introduce the concept of Active Entropy, where the numerical value of Active Entropy serves as a metric for message forwarding. Consequently, the routing algorithm transforms into a limited set of strategies between nodes belonging to different types. This routing algorithm offers numerous advantages including enhanced delivery rate, reduced network overhead ratio and decreased transmission delay. We evaluate and compare the performance of our proposed algorithm with that of DFDL algorithm and Prophet algorithm on the ONE simulation platform. Experimental results demonstrate that our proposed algorithm achieves a delivery rate at least 15% higher compared to the other two algorithms while also reducing overhead ratio.

The existing Intelligent Transportation System (ITS) achieves high success. As an essential component of ITS, Traffic Flow Prediction (TFP) has attracted tremendous attention. It is a critical but challenging task to improve the robust convergence and high accuracy of TFP in real-world scenarios. This study presents an optimized Federated Learning (FL)-based ChebNet model, FedproxChebNet, to realize the highly effective and accurate TFP. By selecting the best penalty constant in the proximal term to optimize the objective function, this model can achieve fast and stable convergence. Using the ChebNet model to aggregate neighbor nodes’ characteristics, more hidden information underlying the spatio-temporal traffic data can be taken into consideration for training the global and local models. All the superiority of the FedproxChebNet model makes it outperform other FL models with the Graph Convolutional Network (GCN), Graph Attention Network (GAT) and Spatio-Temporal Graph Convolutional Network (STGCN). We designed a series of experiments on various FL-based GNN model comparisons, parameter sensitivity tests, and on verifying the performance of FedproxChebNet with different heterogeneous systems with $0\%$, $50\%$ and $90\%$. Based on four real-world data sets from the cognitive network, the experimental results demonstrate that the presented FedproxChebNet provides the best convergence and the highest accuracy in TFP, and achieves the best performance in a highly heterogeneous system ($90\%$). Specifically, the accuracy of FedproxChebNet is at least improved by $3.76\%$ on PeMS07 than other FL-based GNN models. This proposed FedproxChebNet model may be preferable for different scenarios in ITS such as route planning, traffic congestion control and reversible lanes.

In studying ample data security in universities, it is essential to protect the privacy and integrity of data. Current schemes utilize blockchain technology for data sharing, where cloud servers are responsible for storing ciphertext and performing partial encryption and decryption calculations. Data encryption technology can effectively prevent hacker attacks and ensure the integrity of data transmission. However, cloud servers that are only partially trusted may tamper with the ciphertext or return incorrect results. To solve these problems, this paper improves the privacy of access policy, attribute revocation and data authenticity of traditional CP-ABE algorithm. A protection scheme for ample public data security in universities is proposed, and a decentralized network structure based on multiple nodes is designed to improve the efficiency of data queries. The simulation results show that the scheme performs well in the scenario where the number of system attributes is moderate and the complexity of the access policy is not high.

With the widespread adoption of smartphones and the rise of 5G technology, wireless networks fully show their bright future. In order to study the interference factors and optimization methods in the process of wireless communication, this paper studies the wireless communication interference recognition algorithm and power allocation algorithm based on global convolutional neural network, proposes a wireless communication interference recognition system model based on global convolutional neural network, and trains the system. The specific conclusions are as follows: (1) The basic modulation recognition neural network algorithm is constructed based on deep learning theory; (2) As the number of D2D users increases, the time used by the WMMSE algorithm and the equal power allocation algorithm in the traditional method increases. (3) The QL algorithm-based on greedy- is compared with the system-based QL algorithm proposed in this paper. On 200-time nodes, the SINK value of the QL algorithm based on -greedy is increased from 2.6 to 3.3, and the convergence speed is also greatly improved. The system proposed in this paper has a faster learning speed, can accelerate the learning of strategies, and can save a lot of computing resources, and effectively reduce the complexity of operations.

A high voltage gain DC–DC converter with a Y-source network is proposed in this paper for applications such as fuel cells and PV systems. The proposed converter topology is a combination of a Y-source module with a switched capacitor boost module. It is a single switch topology to produce high voltage gain at the load. The superiority of the proposed topology is the high voltage transfer ratio and continuous input current. The voltage gain of the converter can be achieved up to twenty times the input voltage at a duty cycle of 25% itself. The steady state analysis of the converter is carried out using mathematical equations and the working of the converter is explained. The design and analysis of the passive components in the circuit are explained. To illustrate the highlights of the converter, the proposed topology is compared with similar converters in the literature. The simulation of the converter is carried out using MATLAB/SIMULINK. The circuit is verified in the laboratory using a 100W prototype.

Internet of vehicles (IoV) has become an important research topic due to its direct effect on intelligent transportation systems (ITS) development. There are many challenges in the IoV environment, such as communication, big data and best route assigning. In this paper, an effective IoV architecture is proposed. This architecture has four main objectives. The first objective is to utilize a powerful communication scheme in which three tiers of coverage tools — Internet, satellite, high-altitude platform (HAP) — are utilized. Therefore, the vehicles maintain a continuous connection to the IoV environment everywhere. The second objective is to apply filtering and prioritization mechanisms to reduce the detrimental effects of IoV big data. The third objective is to assign the best route for a vehicle after determining its real-time priority. The fourth objective is to analyze the IoV data. The proposed architecture performance is measured using a simulation environment that is created by the NS-3 package. The simulation results proved that the proposed IoV architecture has a positive impact on the IoV environment according to the performance metrics: energy, success rate of route assignment, filtering effect, data loss, delay, usage of coverage tools and throughput.

Wheat head identification and localization are crucial for field management and yield estimation. Traditional wheat head detection relies on labor-intensive manual counting. To address this issue, this study establishes a densely populated wheat head dataset and correspondingly proposes an efficient, rapid real-time model of CB-YOLO, which incorporates a Convolutional Block Attention Module (CBAM) mechanism (a sophisticated fusion of spatial attention mechanism and channel attention mechanism) so as to integrate channel and spatial features. Also, with an incorporated Bidirectional Feature Pyramid Network (BiFPN) to the neck, crowded wheat head detection was enhanced by establishing connections from the backbone to the bottom-up path. This enhancement surpasses the performance of the basic YOLOv5L model, achieving $\mathrm{\text{AP50}}$ of 94.3% and $\mathrm{\text{AP50:95}}$ of 53.9%. Among 10 classical detection models, CB-YOLO has a relatively small parameter size of 44Mb and high computing speed of 108G FLOPs. Additionally, ablation experiments demonstrate that compared to YOLOv5L without CBAM and BiFPN, the feature fusion module improves $\mathrm{\text{AP50}}$ from 93.2% to 94.3%, indicating its effectiveness in enhancing detection performance. In conclusion, CB-YOLO exhibits outstanding identification performance, showing its feasibility in practical agricultural applications, and future work will focus on improving its localization ability.

With the development of internet platforms, consumers increasingly rely on online product reviews during the shopping process. Customer online reviews can guide product design and provide valuable insights for businesses. Therefore, analyzing customer online reviews has become a research hotspot. However, existing studies suffer from some limitations, including the lack of fine-grained sentiment analysis and word clustering analysis. To address these issues, this study proposes a method based on Long Short-Term Memory (LSTM) for identifying and predicting customer preferences, aiming to provide more accurate information support for product design improvement personnel. This research first conducts data collection, preprocessing, and word vector computation. Subsequently, dictionary and sentiment labels are extracted. Based on a topic clustering system, sentiment labels are quantified for polarity classification, and sentiment scores and importance values are calculated as evaluation metrics for customer preference data. The preference-identified data are then applied to an LSTM prediction model, and the dataset is partitioned accordingly. Finally, the trained model is used for LSTM-based prediction of importance values and sentiment scores. The research results demonstrate that this method can accurately predict product preferences based on dynamic online reviews.

Most of the existing research works on stock price prediction ignore the synergistic effect of multi-source factors. Therefore, an enterprise stock price prediction method based on multi-source information fusion based on deep neural network (DNN) is proposed. Based on the condition of multi-source information fusion, the original data related to enterprise stock price are collected from multiple sources, and the structure level and model framework of the method are constructed. The feature extraction technology of DNN is used to extract the features useful for stock price prediction from the pre-processed data, and the DNN structure considering multi-source information fusion is established. Finally, feature extraction and evaluation settings are completed based on data variables. LOSS, ACCURACY and other indicators were used for analysis. The results show that compared with typical prediction methods, this method can make use of multiple information sources more comprehensively and improve the prediction accuracy. In addition, the proposed method has certain flexibility and can adapt to the characteristics and changes of different stock markets

Scoring of subjective question answering costs much human labor in realistic applications. To deal with this issue, we propose to leverage the powerful semantic comprehension capability of the transformer-Bidirectional Encoder Representations from Transformers (BERT)-integrated model, and propose a large language model-based autonomous scoring method for subjective question-answering in the English context. First, a pretrained BERT structure is used to extract features from question sentences, obtaining vector representations of each word. Then, these vectors are input into the transformer encoder to obtain the semantic representation for the whole sentence. Next, the semantic content of subjective questions based on the context can be realized. Finally, we divide the student’s answers into different scoring intervals to obtain the final rating result. Besides, we compared the scoring results with other methods and used the Kaggle competition published dataset, NLPCC DBQA dataset, Text Retrieval Conference QA (TrecQA) dataset, and WikiQA dataset. The experimental results show that our proposal performs well in subjective English question scoring. Compared with traditional manual scoring, this method has achieved significant improvements in scoring efficiency and accuracy. In addition, we also conducted comparative experiments to demonstrate the effectiveness and applicability of the proposal. Through the powerful capabilities of the transformer-BERT-integrated model, the proposed model can accurately capture students’ writing ability and English proficiency.

When an adder circuit, which uses less power and operates at a higher speed, is introduced as a fundamental building block, the multiplier, arithmetic and logic unit (ALU), and digital system’s power delay product (PDP) performance can be easily improved. The graphene nanoribbon field effect transistor (GNRFET) used in very large-scale integrated (VLSI) circuits was developed in the submicron regime and offers superior electrical properties to the MOS transistor. This research paper introduces a full-adder circuit containing twelve GNRFETs (12T GF-FA). Calculations have been made about the introduced 12T GF-FA’s power usage, speed, PDP and leakage power. A few of the existing full adders with 8–32 transistors are compared to the performance of the newly proposed 12T GF-FA in terms of power and delay. For this comparison, some conventional full adders with 8–32 transistors have been implemented using 16nm technology GNRFETs. The pull-down network of the suggested adder has two stacked GNRFETs. The proposed adder’s current conduction and power consumption are reduced by the use of stacked transistors. According to the simulation results, the PDP of the suggested 12T GF-FA is 73.2–99% lower when compared to other full adders considered state-of-the-art. Additionally, it has been researched and documented how variations in the PVT and GNRFET parameters affect the performance of full-adder circuits. The proposed adder, with its low PDP, is especially suitable for VLSI signal processing applications. The simulation was carried out using the HSPICE simulation tool and the 16nm MOS-GNRFET model.

This paper proposes two novel approaches: a signed–unsigned modified Booth decoder/encoder that is used for the production of partial products and a 5-2 compressor for the addition stage of partial products. The improvement of a circuit can be done at the transistor level and the gate level. To improve the circuits at the gate level for the modified Booth decoder/encoder, a new table was designed and also the 5-2 compressor was obtained by changing the truth table. Speed, power consumption and area were improved in the proposed structures. In this paper, at the transistor level, the gate diffusion input (GDI) technique was used to implement logical gates and the gate-level delay of the GDI structures was also calculated. The results indicated that the proposed 5-2 compressor had a delay of 119 ps with a power consumption of 65$\mu$W, which shows a 23.5% improvement in power delay product (PDP) compared to the best structure in the comparison table, whereas the proposed Booth decoder/encoder had a delay of 257 ps with a power consumption of 61.74$\mu$W and shows a 63.7% improvement in PDP compared to previous studies. By using the proposed structures in the multiplier, a 22% improvement in PDP was observed. To simulate the obtained structures, the TSMC 0.18 and 0.09$\mu$m technologies and the HSPICE software were used. Cadence software was used to implement the layouts of the proposed structures.