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This paper presents a new power efficient single ended sense amplifier (SA). The proposed circuit is based on the direct current voltage conversion technique. It has been simulated using Microwind3 and DSCH3 tools (advanced BSIM 4 level) for 90 nm CMOS technology in terms of power consumption, sense time and results were compared to other circuits. The proposed SA circuit consumes more than 50% less power and gives 90% faster sensing speed compared to other circuits. The lower power consumption is due to lower leakage current, lower voltage drop on bit-line and faster speed is due to positive feedback of the circuit. The proposed circuit is more robust against any process and temperature variation.

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the $I_{\mathrm{\text{on}}}/I_{\mathrm{\text{off}}}$ ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiation-hardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages.

With the aggressive growth of the internet of things-based applications in the domestic and industrial domain, the embedded static memory is also under renovation stage to eliminate classical barriers such as soft errors, poor stability, and mediocre performance. In this work, a novel twelve transistors (12T) SRAM cell is presented that replaces the conventional inverter with Schmitt trigger-based inverter in core latch. The proposed SRAM circuit has been compared with four formerly reported designs for investigating the improvement in terms of various performance metrics. These designs include conventional six transistors (6T), tunable transistor 8T (T8T), PPN inverter-based 10T (PP10T), and stable low read power 11T (S11T) cells. The presented cell effectively minimizes the soft errors attributed to $1.36\times$/$1.27\times$/$1.66\times$/$1.27\times$ enhancement of critical charge compared to 6T/T8T/PP10T/S11T cells. Also, the proposed bit-cell effectively mitigates multi-bit-cell upsets because it allows bit interleaving array structure. The presented bit-cell also shows reduction in leakage power by $1.08\times$/$1.33\times$/$0.43\times$/$1.28\times$ in comparison to 6T/T8T/PP10T/S11T cells, respectively. The read and write stability of proposed bit-cell circuit is enhanced by $1.96\times$/$1.88\times$/$1\times$/$1.92\times$ and $1.15\times$/$1.19\times$/$1.29\times$/$1.45\times$, respectively, in comparison to 6T/T8T/PP10T/S11T cells, respectively. In addition to this, proposed cell exhibits improvement in dynamic power, data retention voltage, and overall electrical quality matrix. Variability comparison of key design metrics such as read power and read current of the proposed SRAM circuit with 6T cell has also been presented in this work.

In this paper, a 9T SRAM cell with low power (LP9T) and improved performance has been proposed. This cell is free from half-select issue and works with single-ended read and differential write operation in the sub-threshold region. To evaluate the relative performance, the obtained characteristics of LP9T SRAM cell are compared with other state-of-the-art designs at 45-nm technology node. The read and write power dissipation of LP9T SRAM cell is reduced by $1.65\times$ and $1.84\times$ as compared to Conv.6T SRAM cell. In proposed cell, leakage power is reduced by $1.58\times$, $1.40\times$, $1.47\times$, $1.05\times$, $1.57\times$ and $1.31\times$ as compared to conventional 6T (Conv.6T), low power (LP8T), transmission gate 8T(TG8T), transmission gate 9T (TG9T), Schmitt trigger 9T (ST9T), and positive feedback control 10T (PFC10T) SRAM cells. This reduction in leakage power is attributed to stacking effect. LP9T SRAM cell also exhibits significant improvement in read/write access time as compared to all considered cells. Also, the read and write energy of proposed cell is lowest among all considered cells. The LP9T SRAM cell has $2.2\times$ and $1.63\times$ higher read and write stability as compared to Conv.6T SRAM cell. Proposed SRAM cell has the highest value of ON to OFF current ratio ($I_{\mathrm{\text{on}}}∕I_{\mathrm{\text{off}}}$) which signifies the highest bit-cell density among all considered cells. The LP9T SRAM cell occupies $1.20\times$ large area as compared to Conv.6T SRAM cell. The overall quality of SRAM cell is calculated through the electrical quality metric (EQM). It is observed that LP9T SRAM cell has the highest value of EQM in comparison to considered cells at 0.3V supply voltage.

In this work, a transmission gate-based low-power ten FinFET (TGLP10T) single-ended read/write SRAM cell is proposed. The proposed cell achieves low leakage operation along with improved write-ability. The performance metric results obtained from TGLP10T are compared with five previously published bit-cell designs, i.e., conventional 6T (Con6T), robust transmission gate-based 10T SRAM (RTG10T), transmission gate-based variation resistant 9T SRAM (TGVR9T), PNN (PMOS-NMOS-NMOS) inverter-based 10T (PNN10T) and PPN (PMOS-PMOS-NMOS) inverter-based read decoupled 10T (PPNRD10T. The leakage power in proposed design is reduced by $1.27\times ∕1.15\times ∕1.33\times ∕1.15\times ∕1.00\times$ compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The write power and WSNM are improved by $1.07\times ∕1.40\times ∕0.87\times ∕1.63\times ∕0.78\times$ and $1.57\times ∕1.69\times ∕1.08\times ∕1.59\times ∕1.50\times ∕1.00\times$, respectively, compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The read delay and write delay are improved by $1.00\times ∕1.54\times ∕1.36\times ∕1\times ∕2.83\times$ and 1.68 $\times ∕2.35\times ∕1.82\times ∕2.89\times ∕1.77\times$, respectively, compared to Con6T/RTG10T/TGVR9T/PNN10T/PPNRD10T cells. The proposed design shows the least data retention voltage compared to other SRAM bit-cells.

The intention of this paper is to reduce power and area of 2:1 multiplexer (MUX) while maintaining the competitive performance. The various configurations are designed using different topology of 2:1 MUX such as CMOS-based MUX, transmission gate and pass transistor using fin-shaped field effect transistor (FINFET). The mobility was enhanced in devices with taller fins due to increase tensile stress. In DG, FINFET can be efficiently used to develop performance and reduce power consumption. In noncritical paths self-determining gate control can be used to join together parallel transistors. We have estimated the optimum power, optimum current, leakage power, leakage current, operating power, operating current and delay in voltage supply 0.7 V at different temperature such as 10°C, 27°C and 50°C, respectively. A 20 ns access time and frequency 0.5 GHz provide 45 nm CMOS process technology with 0.7 V power supply is employed to carry out different topology of 2:1 MUX using FINFET.