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A COMPACT MEMORY-FREE ARCHITECTURE FOR THE AES ALGORITHM USING RESOURCE SHARING METHODS

YONG-SUNG JEON

Information Security Research Division, ETRI, 161, Yuseong-Gu, Daejeon, 305-700, Korea

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YOUNG-JIN KIM

Department of Computer Science and Engineering, SunMoon University, Kalsan 100, Tangjeong, Asan, 336-708, Korea

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DONG-HO LEE

School of Electrical Engineering and Computer Science, Kyungpook National University, 1370 Sankyuk-dong, Buk-gu, Daegu, 702-701, Korea

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https://doi.org/10.1142/S0218126610006633Cited by:22 (Source: Crossref)

Abstract

This paper presents a resource-shared 8-bit (RS8) architecture for the AES algorithm, which aims at compacting the hardware architecture and allows hardware resources to be shared efficiently between encryption and decryption without using a memory. The RS8 architecture only requires one combined S-box/S^-1-box for encryption, decryption and key expansion. The RS8 architecture implements the multiplicative inverse in the composite field GF((2⁴)²) with resource sharing methods. In addition, the number of XOR gates used by the proposed combined MixColumns/InvMixColumns module is less than half that of the conventional 32-bit architecture. When comparing the RS8 architecture with the conventional 32-bit architecture on a Xilinx Spartan2 FPGA, the number of total equivalent slices is reduced by 51%. Additionally, the highest operation frequency of the RS8 architecture is 66 MHz, and the throughput is 24 Mbps. Therefore, the performance of the RS8 architecture is sufficient for low-area applications such as wireless network devices and radio frequency identification (RFID).

This paper was recommended by Regional Editor Krishna Shenai.

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