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In this work, engineered nanostructures (ENS) have been fabricated on the packed integrated circuits. Coding lookup tables were developed to assign different digits in numerical matrices to different fabricated nano-signatures. The numerical matrices are encrypted according to advanced encryption standard (AES). The encrypted numerical matrix is ink printed on the components, and the nanosignatures are fabricated on the packaged of the chips via electron beam lithography (EBL). This process is to be done in the manufacturer side of the supply chain. The numerical matrix and the nanosignature accompany the product in its long journey in the global supply chain. The global supply chain is proved to be susceptible to counterfeiters. For keeping counterfeiters‘ hands out of the process, the cipher key and the coding lookup tables are provided to the consumer using a secure direct line between the authentic manufacturer and the consumer. In the consumer side, the printed numerical matrix is decrypted. Having the decrypted numerical matrix makes it possible to extract the nanosignature from the laser speckle pattern shined on the packaged product. In this work, an algorithm is developed to extract the nano-signature by having the decrypted matrix and reflected laser speckle patterns as inputs. Confirming the existence of the nano-signature confirms the authenticity of the component. Imitating the nano-signatures by the counterfeiters is not possible because there is no way for them to observe the shape of these signatures without having access to the cipher key.

Experimental formation of LPO (liquid phase oxidation)-grown InGaP native oxide near room temperature (~60°C) is demonstrated. A high oxidation rate is obtained and checked by SEM and AES. The native oxide is determined to be composed of InPO₄ and Ga₂O₃, analyzed by the results of XPS measurement. Due to the presence of the excellent quality of InGaP native oxide, high hydrogen (H₂) sensitivity in output current of a Pd/oxide/InGaP MOS Schottky diode is observed. Under the applied voltage of -1 V and 50 ppm H₂/air, a high sensitivity of 1090 is obtained. An obvious variation of output current and a short response time due to the exposure to different H₂ concentration are also achieved. For example, the adsorption (τ_a) and desorption (τ_b) time constants under 50 ppm H₂/air are 2.3 s and 2.7 s, respectively.

Optimized implementation of computationally intensive cryptographic transformation is an area of active research, mainly focused on Advanced Encryption Standard (AES). Byte substitution implemented using substitution boxes (S-boxes), is the main transformation in AES which strains the enabling embedded platform, e.g., Field Programmable Gate Arrays. We represent a novel clocking technique enabling optimized implementation of Byte Substitution that enhances processing speed and reduces the area required for S-boxes on Xilinx FPGA Block RAM (BRAM).

This paper presents a resource-shared 8-bit (RS8) architecture for the AES algorithm, which aims at compacting the hardware architecture and allows hardware resources to be shared efficiently between encryption and decryption without using a memory. The RS8 architecture only requires one combined S-box/S^-1-box for encryption, decryption and key expansion. The RS8 architecture implements the multiplicative inverse in the composite field GF((2⁴)²) with resource sharing methods. In addition, the number of XOR gates used by the proposed combined MixColumns/InvMixColumns module is less than half that of the conventional 32-bit architecture. When comparing the RS8 architecture with the conventional 32-bit architecture on a Xilinx Spartan2 FPGA, the number of total equivalent slices is reduced by 51%. Additionally, the highest operation frequency of the RS8 architecture is 66 MHz, and the throughput is 24 Mbps. Therefore, the performance of the RS8 architecture is sufficient for low-area applications such as wireless network devices and radio frequency identification (RFID).

Embedded processor is often expected to achieve a higher security with good performance and economical use of resource. However, the choice regarding the best solution for how cryptographic algorithms are incorporated in processor core is one of the most challenging assignments a designer has to face. This paper presents an inexpensive instruction set extensions (ISE) of efficient cryptographic algorithms on 32-bit processors assuring various types of instruction (public/private key cryptography, random number generator (RNG) and secure hash function (SHF)). These extensions provide hardware instructions that implement a full algorithm in a single instruction. Our enhanced LEON2 SPARC V8 core with cryptographic ISE is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40-nm technology. The total area of the resulting chip is about 1.93 mm² and the estimated power consumption of the chip is 16.3 mW at 10 MHz. Hardware cost and power consumption evaluation are provided for different clock frequencies and the achieved results show that our circuit is able to be arranged in many security constrained devices.

This paper presents high throughput iterative and pipelined VLSI architectures of the Advanced encryption standard (AES) algorithm based on composite field arithmetic in polynomial basis. A logical rearrangement has been performed in the byte substitution (S-box) module to reduce the number of gates in the critical path. Also, inversion in GF(2⁴) module has been separately optimized. ASIC implementation of our S-box has comparatively low power and low energy consumption. The iterative and pipelined implementations of AES in field programmable gate array (FPGA) and ASIC using proposed S-box have high hardware efficiency in terms of throughput per unit area (slices in FPGA).

Advanced Encryption Standard (AES) is the most popular symmetric encryption method, which encrypts streams of data by using symmetric keys. The current preferable AES architectures employ effective methods to achieve two important goals: protection against power analysis attacks and high-throughput. Based on a different architectural point of view, we implement a particular parallel architecture for the latter goal, which is capable of implementing a more efficient pipelining in field-programmable gate array (FPGA). In this regard, all intermediate registers which have a role for unrolling the main loop will be removed. Also, instead of unrolling the main loop of AES algorithm, we implement pipelining structure by replicating nonpipelined AES architectures and using an auto-assigner mechanism for each AES block. By implementing the new pipelined architecture, we achieve two valuable advantages: (a) solving single point of failure problem when one of the replicated parts is faulty and (b) deploying the proposed design as a fault tolerant AES architecture. In addition, we put emphasis on area optimization for all four AES main functions to reduce the overhead associated with AES block replication. The simulation results show that the maximum frequency of our proposed AES architecture is 675.62MHz, and for AES128 the throughput is 86.5Gbps which is 30.9% better than its closest existing competitor.

Cryptography has an important role in data security against known attacks and decreases or limits the risks of hacking information, especially with rapid growth in communication techniques. In the recent years, we have noticed an increasing requirement to implement cryptographic algorithms in fast rising high-speed network applications. In this paper, we present high throughput efficient hardware implementations of Advanced Encryption Standard (AES) cryptographic algorithm. We have adopted pipeline technique in order to increase the speed and the maximum operating frequency. Therefore, registers are inserted in optimal placements. Furthermore, we have proposed 5-stage pipeline S-box design using combinational logic to reach further speed. In addition, efficient key expansion architecture suitable for our proposed design is also presented. In order to secure the hardware implementation against side-channel attacks, masked S-box is introduced. The implementations had been successfully done by virtex-6 (xc6vlx240t) Field-Programmable Gate Array (FPGA) device using Xilinx ISE 14.7. Our proposed unmasked and masked architectures are very fast, they achieve a throughput of 93.73 Gbps and 58.57 Gbps, respectively. The obtained results are competitive in comparison with the implementations reported in the literature.

Recently, many organizations and industries are using the cloud computing technologies for exchanging the resources and their confidential data. For this purpose, many cloud services are available and also provide the facility to categorize their users as private and public users for accessing their own data from private cloud and public cloud. The combination of these two clouds is called federated cloud which facilitates to allow both kinds of cloud users for accessing their own data on same cloud database. In this scenario, the authorization and authentication process is becoming complex task on cloud. For providing the facility to access their own data only from federated cloud, a new secured data storage and retrieval algorithm called AES and Triple-DES-based Secured Storage and Retrieval Algorithm (ATDSRA) are proposed for storing the private and public cloud user’s data securely on cloud database. Here, the TDES is used for encrypting the input data, data merging and aggregation methods were used for grouping the encrypted input data. Moreover, a new dynamic data auditing scheme called CRT-based Dynamic Data Auditing Algorithm (CRTDDA) is proposed for conducting the cloud data auditing over the federated cloud and also restricting the data access. The proposed new auditing mechanism that is able to protect the stored data from access violence. In addition, the standard Table64 is used for encryption and decryption processes. The experimental results of this work proves the efficiency of the proposed model in terms of security level.

This paper deals with the design of a true random number generator (TRNG) using the fingerprint as an entropy source and its implementation in substitution box (S-box) of Advanced Encryption Standard (AES). Considering fingerprint as a unique and random arrangement of minutiae, these minutiae points are used as the source of entropy. The proposed design utilizes fewer resources minimizing hardware redundancy and enhancing the level of randomness. This TRNG has been designed and validated using Artix-7 FPGA. The data rate, speed and latency have been obtained as 40 Mbps, 5 Mbps and 305 ns, respectively. The generated random bit stream had also been sampled and converted to a binary format in MATLAB and tested through the National Institute of Standards and Technology (NIST) 800.22 statistical suite for validation. The proposed TRNG design pass efficiency achieved is more than 95% for a sample size of 10 binary sequences.

Thermal decomposition and desorption of dimethylaminoethanol [dmaeH, (CH₃)₂NC₂H₄OH] on Si(100) was studied using temperature-programmed desorption (TPD) and Auger electron spectroscopy (AES). During heating of the sample up to 1100 K, methyliminoacetaldehyde, ethylene, carbon monoxide and hydrogen molecule were desorbed as the main desorption products from dmaeH on Si(100). After TPD experiments, carbon and nitrogen were detected by AES, indicating that complete decomposition of dmaeH also proceeded on Si(100).

We have investigated the effect of Bi on the heteroepitaxial growth of Co on Cu by reflection high-energy electron diffraction (RHEED) measurements. It was found that Bi enhanced the layer-by-layer growth of Co on the Cu(111) surfaces at 100°C. The dependence of the growth on Bi layer thickness suggested that there existed a suitable amount of Bi surfactant layer that enhanced smoother layered growth. On the contrary, for the case of Co growth on Cu(100), Bi depressed the layer-by-layer growth of Co on Cu(100). The surface segregation effect of Bi was also studied by Auger electron spectroscopy (AES).

In this paper, we study the kinetics of potassium adsorption on SrTiO₃(100) surface at room temperature. The study took place in UHV using AES, EELS, LEED, TPD, and WF measurements. Potassium grows in two-dimensional islands with maximum coverage of 3.9 × 10¹⁴ at/cm². During adsorption charge transfer from the K-4s to Ti-3d energy level has been observed. No K–O compound has been measured. After heating at 1050 K most of the adsorbed potassium desorbs and the SrTiO₃(100) (1 × 1) LEED pattern reappears. There is not any indication of potassium intercalation into the substrate, either at room or at elevated temperature.

The surface of materials plays an important role in their technological applications. In the interest to study the stability of materials and their behavior, we irradiate them by the electrons by using the electron spectroscopy such as the Auger electron spectroscopy (AES) and the electron energy loss spectroscopy (EELS). These methods have proved their good sensitivity to study material surfaces. In this paper, we give some results about the effect of the electron beam irradiating the compounds InP, InSb, InPO₄ and In_xGa_1-xAs. The III–V semiconductors InP and InSb seem to be sensitive to the electron irradiation. This breaks the chemical bonds between the element III and V which leads to an oxidation process at the surface. The AES and EELS spectroscopy are also used to characterize the oxide InPO₄ whose thickness is about 10 Å grown on the substrate InP(100). The irradiation of the system InPO₄/InP(100) by the electron beam of 5 keV energy leads to a structural change of the surface, so that there is breaking of chemical bonds between indium and phosphorus (In–P) and formation of new oxide other than InPO₄. In this study we show an important result concerning the effect of the electron beam on the compound In_xGa_1-xAs by varying the parameter x to obtain In_0.2Ga_0.8As and In_0.53Ga_0.47As. It appears that the electron beam affects In_0.2Ga_0.8As too much in comparison with In_0.53Ga_0.47As. In the case of the irradiation of In_0.2Ga_0.8As, there is breaking of chemical bonds between indium and GaAs leading to formation of indium oxide associated to GaAs.

Recently, the development of indium oxide such as In₂O₃ on the III–V semiconductors shows successful technological applications as in the gas sensor field, the emission devices, the biotechnology, etc. The indium oxide In₂O₃ attracted considerable research due to many methods of its synthesis. In our study, we were interested in developing the indium oxide In₂O₃ on the In metal and InSb surfaces by electron beam stimulated oxidation. The formation of In₂O₃ on InSb was advantaged by a previous treatment due to the sputtering of the surface by the argon ions at low energy 300 eV with a current density 2 μA/cm² followed by heating in UHV at 300°C. Our results were monitored by the analysis techniques including the Auger electron spectroscopy (AES) and the electron energy loss spectroscopy (EELS) well suited to study the surface with respect to physical structure and chemical composition.

The key-scheduling algorithm in the AES is the component responsible for selecting from the master key the sequence of round keys to be xor-ed to the partially encrypted state at each iteration. We consider here the group $\mathrm{\Gamma }$ generated by the action of the AES-128 key-scheduling operation, and we prove that the smallest group containing $\mathrm{\Gamma }$ and all the translations of the message space is primitive. As a consequence, we obtain that no linear partition of the message space can be invariant under its action.

With the looming quantum computer threat, the National Institute of Science and Technology (NIST) has done an exhaustive search for both quantum resilient encryption, creating new asymmetric algorithms and a separate “lightweight cryptography” suitable for small IoT electronics, selecting ASCON. However, NIST admits that ASCON is only quasi-quantum resilient. AES has also been independently declared quantum resilient. Unfortunately, the four selected quantum resilient asymmetric algorithms and AES are far too computationally heavy for FinTech smart cards’ use. The proposed Randomization Data Handshake (RDH) has been designed to wrap around both ASCON (and AES) allowing each to create and exchange instructions to build their own non-transmitted quantum resilient session keys using 100% randomized data, while simultaneously authenticating both sender and receiver. Furthermore, credit cards, debit cards, PINs, passwords and session keys are never transmitted. In a way, RDH emulates the quantum entanglement’s ability to exchange data (keys) without sending the data.

In this modern era, malware has emerged as a malicious cyber threat to critical information and communication infrastructure. Ransomware is a type of malware which holds the victim’s computer hostage by encrypting the data available on it, which makes the data unusable and inaccessible to its legitimate user. The attacker demands that the user pay before the decryption key is released to reverse the attack. This chapter explains about ransomware and its classification, how it impacts different platforms, the severity of ransomware, the methodology used by ransomware to penetrate target machines, the attack vectors used, the latest ransomware attacks, the most common targets of ransomware attacks, how to prevent ransomware attacks, and ways to recover.

A reconfigurable cipher chip has higher security and flexibility than a conventional one. Therefore, it will be an important part of the future security mechanisms. For designing such kind of chips, the challenge is to improve the throughput rate. In this paper, the reconfiguration of DES, 3DES and AES is analyzed firstly. Then, it proposes a new reconfigurable architecture based on pipelining and paralleling which can implement the three algorithms with a high-speed. The results show that the operating frequency is 100MHz and the throughput rate is 7Gbps for DES, 2.3Gbps for 3DES and 1.4Gbps for AES. Compared with the similar existing implementations, our design can achieve a higher performance.

In this work, engineered nanostructures (ENS) have been fabricated on the packed integrated circuits. Coding lookup tables were developed to assign different digits in numerical matrices to different fabricated nano-signatures. The numerical matrices are encrypted according to advanced encryption standard (AES). The encrypted numerical matrix is ink printed on the components, and the nanosignatures are fabricated on the packaged of the chips via electron beam lithography (EBL). This process is to be done in the manufacturer side of the supply chain. The numerical matrix and the nanosignature accompany the product in its long journey in the global supply chain. The global supply chain is proved to be susceptible to counterfeiters. For keeping counterfeiters hands out of the process, the cipher key and the coding lookup tables are provided to the consumer using a secure direct line between the authentic manufacturer and the consumer. In the consumer side, the printed numerical matrix is decrypted. Having the decrypted numerical matrix makes it possible to extract the nanosignature from the laser speckle pattern shined on the packaged product. In this work, an algorithm is developed to extract the nano-signature by having the decrypted matrix and reflected laser speckle patterns as inputs. Confirming the existence of the nano-signature confirms the authenticity of the component. Imitating the nano-signatures by the counterfeiters is not possible because there is no way for them to observe the shape of these signatures without having access to the cipher key.