No Access

Enhancing a 32-Bit Processor Core with Efficient Cryptographic Instructions

Electronics and Micro-Electronics Laboratory (E. μ. E. L), Physics Department, Faculty of Sciences of Monastir, University of Monastir, Monastir 5019, Tunisia

Search for more papers by this author

Wajih Elhadjyoussef

Electronics and Micro-Electronics Laboratory (E. μ. E. L), Physics Department, Faculty of Sciences of Monastir, University of Monastir, Monastir 5019, Tunisia

Corresponding author.

Search for more papers by this author

Mohsen Machhout

Electronics and Micro-Electronics Laboratory (E. μ. E. L), Physics Department, Faculty of Sciences of Monastir, University of Monastir, Monastir 5019, Tunisia

Search for more papers by this author

Rached Tourki

Electronics and Micro-Electronics Laboratory (E. μ. E. L), Physics Department, Faculty of Sciences of Monastir, University of Monastir, Monastir 5019, Tunisia

Search for more papers by this author

, and

Kholdoun Torki

Circuits Multi-Project (CMP), 46, Avenue Félix Viallet, 38031 Grenoble Cedex, France

Search for more papers by this author

https://doi.org/10.1142/S0218126615501583Cited by:1 (Source: Crossref)

Abstract

Embedded processor is often expected to achieve a higher security with good performance and economical use of resource. However, the choice regarding the best solution for how cryptographic algorithms are incorporated in processor core is one of the most challenging assignments a designer has to face. This paper presents an inexpensive instruction set extensions (ISE) of efficient cryptographic algorithms on 32-bit processors assuring various types of instruction (public/private key cryptography, random number generator (RNG) and secure hash function (SHF)). These extensions provide hardware instructions that implement a full algorithm in a single instruction. Our enhanced LEON2 SPARC V8 core with cryptographic ISE is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40-nm technology. The total area of the resulting chip is about 1.93 mm² and the estimated power consumption of the chip is 16.3 mW at 10 MHz. Hardware cost and power consumption evaluation are provided for different clock frequencies and the achieved results show that our circuit is able to be arranged in many security constrained devices.

This paper was recommended by Regional Editor Emre Salman.

Keywords:

References

M. O'Neill and M. J. B. Robshaw , IET Comput. Digit. Tech. 4 , 14 ( 2010 ) . Crossref, Web of Science, Google Scholar
N. Benhadjyoussefet al., A compact implementation of AES on 32-bit platforms, 17th Int. Conf. Design and Technology of Integrated Systems in Nanoscale Era (DTIS'2012) (2012) pp. 16–18. Google Scholar
SAPRC International, SPARC architectual manual (1992), version 8, SPARC International, Inc., Campbell, CA . Google Scholar
X. Zeng, C. Chen and Q. Zhang, A reconfigurable public-key cryptography coprocessor, Proc. 2004 IEEE Asia-Pacific Conf. Advanced System Integrated Circuits (2004) pp. 172–175. Google Scholar
C. Nathan et al. , ACM SIGARCH Comput. Archit. News 33 , 272 ( 2005 ) . Crossref, Google Scholar
I. Paolo and L. Rainer , Customizable Embedded Processors: Design Technologies and Applications ( Elsevier , 2007 ) . Google Scholar
C.-C. Chia and S.-S. Wang , Efficient design of an embedded microcontroller for advanced encryption standard , Proc. 2005 Workshop Consumer Electronics and Signal Processing (WCESP) ( 2005 ) , http://www.mee.chu.edu.tw/labweb/WCEsp2005/96.pdf . Google Scholar
S. O'Melia and A. Elbirt , Instruction set extensions for enhancing the performance of symmetric-key cryptography , IEEE Annu. Computer Security Applications Conf. ( 2008 ) . Google Scholar
K. Nadehara, M. Ikekawa and I. Kuroda, Extended instructions for the AES cryptography and their efficient implementation, IEEE Workshop Signal Processing Systems (SIPS'04) (2004) pp. 152–157. Google Scholar
G. Bertoniet al., Speeding up AES by extending a 32-bit processor instruction set, Proc. 17th IEEE Int. Conf. Application-Specific Systems, Architectures and Processors (ASAP 2006) (2006) pp. 275–282. Google Scholar
ISO/IEC 7816: Smart cards standards, International Organization for Standardization, Geneva . Google Scholar
S. Tillich and J. Großschädl, Instructions set extensions for efficient AES implementation on 32-bit processors, Lecture Notes in Computer Science, Cryptographic Hardware and Embedded Systems: CHES 20064249 (2006) pp. 270–284. Google Scholar
A. J. Elbirt, Fast and efficient implementation of AES via instruction set extensions, Proc. 21st Int. Conf. Advanced Information Networking and Applications Workshops (AINAW 2007) (2007) pp. 481–490. Google Scholar
S. Tillich and C. Herbst, Boosting AES performance on a tiny processor core, Topics in Cryptology: CT-RSA 20084964, Lecture Notes in Computer Science (2008) pp. 170–186. Google Scholar
M.-K. Leeet al., Information Security Applications, Lecture Notes in Computer Science 3786 (Springer-Verlag, 2006) pp. 207–217. Crossref, Google Scholar
A. E. Cohen and K. K. Parhi , J. Signal Process. Syst. 60 , 31 ( 2003 ) . Crossref, Web of Science, Google Scholar
S. Bartolini et al. , IEEE Trans. Comput. 57 , 679 ( 2008 ) . Crossref, Web of Science, Google Scholar
ISO, ISO/IEC 14443: Identification cards — Contactless integrated circuit cards — Proximity cards, International Organization for Standardization, Geneva . Google Scholar
P. Bennati, R. Giorgi and E. Martinelli, Elliptic curve cryptography support for ARM based embedded systems, HiPEAC ACACES-2006 (2006) pp. 13–16. Google Scholar
H. Eberleet al., Architectural extensions for elliptic curve cryptography over GF(2m) on 8-bit microprocessors, Proc. 16th IEEE Int. Conf. Application-Specific Systems, Architectures and Processors (ASAP 2005) (2005) pp. 343–349. Google Scholar
M. Drutarovsky and M. Varchola, Cryptographic system on a chip based on Actel ARM7 soft-core with embedded true random number generator, Proc. 11th IEEE Workshop Design and Diagnostics of Electronic Circuits and Systems (DDECS'08) (2008) pp. 164–169. Google Scholar
S. Tillich and J. Großschädl, VLSI implementation of a functional unit to accelerate ECC and AES on 32-bit processors, Proc. First Int. Workshop Arithmetic of Finite Fields (WAIFI 2007) (2007) pp. 40–54. Google Scholar
P. Grabher, J. Großschädl and P. Dan, Light-weight instruction set extensions for bit-sliced cryptography, Cryptographic Hardware and Embedded Systems: CHES 20085154, Lecture Notes in Computer Science (2008) pp. 331–345. Google Scholar
V. Tobias, P. Dan and J. Großschädl, Instruction set extensions for pairing-based cryptography, Pairing-Based Cryptography: pairing 20074575, Lecture Notes in Computer Science (Springer-Verlag, 2007) pp. 208–224. Google Scholar
J. Großschädl, S. Tillich and A. Szekely, Performance evaluation of instruction set extensions for long integer modular arithmetic on a SPARC V8 processor, Proc. 10th Euromicro Conf. Digital System Design Architectures, Methods and Tools (DSD 2007) (2007) pp. 680–689. Google Scholar
Gaisler Research, LEON2 processor users manual: XST edition (2005), Version 1.0.30, http://www.gaisler.com/doc/leon2-1.0.30-xst.pdf . Google Scholar
NIST, FIPS Pub 197: Advanced encryption standard (AES), Federal information processing standards publication, Information Technology Laboratory (ITL), National Institute of Standards and Technology (NIST), Gaithersburg, MD, USA . Google Scholar
NIST, FIPS Pub 186-3: Digital signature standard (DSS), Federal information processing standards publication, Information Technology Laboratory, National Institute of Standards and Technology (NIST), Gaithersburg, MD, USA . Google Scholar
NIST, Secure hash standard: FIPS PUB 180-1, National Institute of Standards and Technology, Gaithersburg, MD, USA . Google Scholar
P. Kitsoset al., Comparison of the hardware architectures and FPGA implementations of stream ciphers, Proc. 2004 11th IEEE Int. Conf. Electronics, Circuits and Systems (ICECS 2004) (2004) pp. 571–574. Google Scholar
N. Benhadjyoussefet al., A cryptographic processor for 32-bit embedded system with resource-constraints,, Int. Rev. Comput. Softw. (IRECOS)8 (2013) pp. 132–143. Google Scholar
Xilink, Virtex-5 FPGA Family Datasheet (2007), Xilinx, Inc., San Jose, CA, USA . Google Scholar
A. Hodjat and I. Verbauwhede, Interfacing a high speed crypto accelerator to an embedded CPU, Conf. Record Thirty-Eighth Asilomar Conf. Signals, Systems and Computers1 (2004) pp. 488–492. Google Scholar
P. Schaumontet al., Embedded software integration for coarse-grain reconfigurable systems, Proc. 18th Int. Parallel and Distributed Processing Symp. (IPDPS'04) (2004) pp. 137–142. Google Scholar
N. Sklavos , Inf. Secur. J.: A Glob. Perspect. 19 , 53 ( 2010 ) . Crossref, Google Scholar
Altera, 40-nm FPGA power management and advantages (2008), White Paper, http://www.altera.com/literature/wp/wp-01059-stratix-iv-40nm-power-management.pdf . Google Scholar
C. Hocquet et al. , J. Cryptogr. Eng. 1 , 79 ( 2011 ) . Crossref, Google Scholar
M. Hutter, M. Feldhofer and T. Plos, An ECDSA processor for RFID authentication, Revised Selected Papers 6th Int. Workshop Radio Frequency Identification: Security and Privacy Issues (RFIDSec'10), pp. 189–202 . Google Scholar
NIST, Special publication 800-57: Recommendation for key management — Part 1: General guideline, Draft 2003, Information Technology Laboratory, National Institute of Standards and Technology, Gaithersburg, MD, USA . Google Scholar
P. Kiatiseviet al., Development of an audio player as system-on-a-chip using an open source platform, IEEE Int. Symp. Circuits and Systems (ISCAS 2005) (2005) pp. 2935–2938. Google Scholar
D. Mattisson and M. Christensson, Evaluation of synthesizable CPU cores, Computer Science and Engineering Program, Department of Computer Engineering, Chalmers University of Technology (2004) . Google Scholar
M. Raymond and G. David, A program generator for Intel AES-NI instructions, Progress in Cryptology — INDOCRYPT 20106498, Lecture Notes in Computer Science (Springer, 2010) pp. 311–327. Google Scholar
D. Cheresiz et al. , IEEE Trans. Very Large Scale Integr. (VLSI) syst. 13 , 1 ( 2005 ) . Crossref, Web of Science, Google Scholar
S. Mangard , E. Oswald and T. Popp , Power Analysis Attacks: Revealing the Secrets of Smart Cards ( Springer-Verlag , 2007 ) . Google Scholar
D. Gullasch, E. Bangerter and S. Krenn, Cache games bringing access-based cache attacks on aes to practice, Proc. 2011 IEEE Security and Privacy (2011) pp. 490–505. Google Scholar
A. P. de Oliveira and E. D. Moreno , Impact of the DES and AES algorithms on PERS (A specific processor for sensor networks) , Second Int. Conf. Systems and Networks Communications ( 2007 ) . Google Scholar
G. S. Quirino and E. D. Moreno , Int. J. Electron. Electr. Eng. 1 , 39 ( 2013 ) . Crossref, Google Scholar
D. Sauveronet al., Computational Intelligence in Information Assurance and Security (Springer, 2007) pp. 201–237. Google Scholar
S. Abughazalah, K. Markantonakis and K. Mayes, Data Privacy Management, Autonomous Spontaneous Security, and Security Assurance (Springer International Publishing, 2015) pp. 147–164. Crossref, Google Scholar
S. Chaumette and D. Sauveron, Secure Smart Embedded Devices, Platforms and Applications (Springer-Verlag, New York, 2014) pp. 335–350. Crossref, Google Scholar