Journal of Circuits, Systems and Computers

In this paper, a more realistic analytical model for randomly distributed mixed carbon nanotube (CNT) bundle (MCB) is presented for the analysis of crosstalk induced delay. Several researchers have proposed analytical models for interconnects based on single-walled CNT (SWCNT), multi-walled CNT (MWCNT) bundle and most interestingly, spatially arranged mixed CNTs. Although, bundled SWCNTs and MWCNTs are easily realizable, but, practically it is almost impossible to fabricate a MCB with precise arrangements of SWCNTs and MWCNTs. Motivated by these facts, this paper presents a corner placement algorithm for randomly distributed SWCNTs and MWCNTs of different diameters in a MCB. The performance of MCB is compared with that of conventional bundled SWCNT and bundled MWCNT at different coupled interconnect lengths and spacing. Encouragingly, for a fixed cross-sectional area, the overall crosstalk induced delay of MCB reduces by 65.03% and 23.54% in comparison to the bundles having either SWCNTs or MWCNTs with smaller diameters, respectively. However, in contradiction to most of the previously reported results, bundled MWCNTs with larger diameters outperform the randomly distributed MCBs in terms of crosstalk performance.

Low output frequency and spurs are main imperfections in direct digital frequency synthesis (DDFS). For increasing output frequency determined by sampling rate, the structure of multi-path pseudo-interleaved DDFS is proposed. However, it introduces more complex phase truncation error than single path DDFS. In order to analyze the effect of phase truncation error, the model of pseudo-interleaved DDFS with phase truncation is established. Based on the model, the distribution and amplitude of spur caused by phase truncation are discussed and calculated. Then some important conclusions are drawn and proved by experiment, which can provide theoretical supports for spurious performance evaluation and parameter selection while designing signal source or clock generator based on pseudo-interleaved DDFS.

In this paper, we proposed a novel relaxation oscillator to address the frequency variation caused by the comparator delay. The conventional operational transconductance amplifiers (OTAs)-comparator is replaced with a Schmitt trigger to significantly reduce the delay. This Schmitt trigger is implemented by a differential structure operating in the subthreshold region to generate a proportional to absolute temperature (PTAT) hysteresis. Both the voltage reference and the current source are made PTAT as well. The proposed oscillator can be made ultra-low power and have excellent frequency stability over process, voltage and temperature (PVT) variation.

We study the principle of least (stationary) action for mem-elements. The least action principle allows us to derive relationships between the electrical variables for each of the six mem-elements. The principle of least action from modern physics is a natural environment to characterize mem-elements, including various one-period loops in the context of periodic circuits. The time-integrals of Lagrangian lead to the action and coaction quantities and a full characterization of mem-elements with periodic control variables.

Ultra-wideband (UWB) technology is very suitable for indoor wireless localization and ranging. IEEE 802.15.4a is the first physical layer standard specifically developed for wireless ranging and positioning. While malicious devices are not typically present, snoopers, impostors and jammers can exist. The data link and network layers in standards such as Wi-Fi, IEEE 802.15.4 and 802.11 mainly provide authentication and encryption support, but security about ranging or location is rarely considered. Ranging can be achieved using just the preamble and start of frame delimiter (SFD), so in this case malicious devices can easily obtain position information. Therefore, the security of ranging or positioning protocols is very important, which differs from the case with data exchange protocols. To provide secure location services, a protocol is presented which is based on a pseudo-random turnaround delay. In this protocol, devices use different turnaround times so that it is difficult for a snooper to figure out the location of sensor devices in protected areas. At the same time, in the period of Hello frame transmission, together with the authentication mechanism of IEEE 802.15.4, an impostor cannot easily engages its deception attack.

Fast growing technologies have made pervasive computing elements part of our routine life. These computing elements dissipate a lot of energy, and power optimization is one of the critical design aspects of such systems. In this work an intelligent laboratory automation and resource management system (iLARMS) is proposed, which incorporates power-aware strategies activated in software with hardware support. In the current work, investigations are carried out to observe the energy issues of the application and the processors used. Various software techniques for energy saving are incorporated in the application level and in the processor core level. The hardware implementation of the proposed resource management system is carried out using PIC16F877A and ARM7 LPC2148 microcontrollers and Intel Core 2 Duo processors. An average energy saving of the order of 48.78% was achieved with iLARMS when compared to a conventional resource management system.

In this paper, we propose a unified architecture for computation of double-precision floating-point division, reciprocal, square root, inverse square root and multiplication with a significant area reduction. First, a double-precision multiplication-based divider, the common datapath shared with these arithmetic computations, is optimized by a modified Goldschmidt algorithm to achieve better area efficiency. In this algorithm, a linear-degree minimax approximation instead of second-degree is used to obtain a 15-bit precision estimate of the reciprocal so that we can get a rather small lookup table (LUT) as well as reduced amount of computation when accumulating the partial products. Two Goldschmidt iterations specially designed for hardware reuse are performed to gain the final accurate result of division. By virtue of the pipelined processing, the time cost for the two iterations is minimized. Second, a reconfigurable datapath with a little extra area cost is introduced to dynamically support multiple double-precision computations by executing the optimized divider iteratively. The design is finally implemented and synthesized in SMIC 0.13-μm CMOS process. The experimental results show that the proposed design can achieve a speed of 400 MHz with area of 61.6 K logic gates and 9-Kb LUT. Compared with other works, the area efficiency (performance/area ratio) of the proposed unified architecture is increased by about 20% in average, which is a better performance-area trade-off for embedded microprocessors.

This paper proposes a high data rate, low-power, low-voltage design of OTA-based M-ary ASK, FSK and QAM modulator and demodulator circuits. Conventional D/A converter of M-ary circuit has been replaced with the operational transconductance amplifier-based n-bits to 2ⁿ level converter which operates with input frequencies up to 2.1 GHz. OTA-based oscillator and PLL is being designed for high speed M-ary FSK. Eye diagram analysis has been carried out, conforming a very low signal distortion. Theoretical analysis of bit error rate has been done. The circuit analysis and simulation results confirm the reliability and accuracy of the design. Effective layouts and die photographs of the proposed designs are also presented.

Quantum-dot Cellular Automata (QCA) is an attractive nanoelectronics paradigm which is widely advocated as a possible replacement of conventional CMOS technology. Designing memory cells is a very interesting field of research in QCA domain. In this paper, we are going to propose novel nanotechnology-compatible designs based on the majority gate structures. In the first step, this objective is accomplished by QCA implementation of two well-organized JK flip-flop designs and in the second step; synchronous counters with different sizes are presented as an application. To evaluate functional correctness of the proposed designs and compare with state-of-the-art, QCADesigner tool is employed.

This paper proposes a switched-capacitor (SC)-based step-down AC–DC power converter with high-frequency feed without rectifier or transformer. The operational principle of the circuits and the design considerations are described. The main advantage of the circuit is that step-down voltage can be achieved in the circuit by simply configuring with cascaded stages, which will be much more convenient to be modular development and easy for replacement and maintenance; the voltage and current stresses of most components are smaller than the conventional converter. Using buffer capacitor to reserve energy, there are no magnetic energy storage elements in the circuits. Weight and size can be further reduced due to high-frequency-power line operation. Zero current switching (ZCS) is achieved by introducing small resonant inductors. Therefore, higher efficiency and power density can be achieved. The performance of the converter has been demonstrated by an experiment with 50 kHz 50 V power feed which is emulated by a signal generator and high-frequency amplifier to prove the concept.

This paper presents an energy-efficient and high linearity temperature sensor based on the architecture of a simple on-chip oscillator. A self-calibrated block is proposed to compensate the non-linearities of the on-chip oscillator due to PVT variations. In this manner, this on-chip oscillator-based temperature sensor has superior performance over the conventional inverter-chain-based types. In order to generalize the application, no highly linear temperature coefficient resistors are being utilized. The entire circuit is simple and easy to be scaled down. According to the verifications in 65 nm CMOS process, with one-point calibration, this temperature sensor can achieve an inaccuracy within ±1°C in the temperature range from -55°C to 125°C, with a power consumption of only 0.6 μA under 1.2 V supply voltages.

A new structure of Boost Cascaded DC Link H-Bridge Inverter (BCDCLHBI) is proposed for domestic UPS applications. It consists of DC-DC converter, sub-multilevel modules and H-bridge inverter circuits. The proposed sub-multilevel modules synthesize a stepped DC link voltage with reduced voltage stress across the H-bridge inverter. Compared with conventional two-level inverter the proposed stepped DC link inverter configuration has reduced Power Spectral Density (PSD) and reduced voltage stress. Compared with conventional Cascaded Multilevel Inverter (CMLI) configuration, the proposed system has reduced power switches, DC sources and gate driver requirements. To obtain better quality of AC power output, carrier-level shifted Pulse Width Modulation (PWM) schemes are developed for sub-multilevel switching. A simulation and prototype model of 7-level BCDCLHBI is developed and its performance is validated.

A novel low-power edge detection circuit is presented in this work. Upon the arrival of signal falling edge, the proposed design establishes a small voltage difference between the gate and source terminals of a MOS transistor which slightly increases the MOS transistor leakage current. A current integration-based approach is used to robustly sense the current change and subsequently detect the signal falling edge. The design is suitable for ultra-low-power sensor wake-up circuits. Design guidelines for achieving optimal detection sensitivity as well as the implementation of calibration circuits for coping with process variations and mismatches are discussed in the paper. Simulation results are presented to demonstrate the performance of the proposed circuit.

Embedded processor is often expected to achieve a higher security with good performance and economical use of resource. However, the choice regarding the best solution for how cryptographic algorithms are incorporated in processor core is one of the most challenging assignments a designer has to face. This paper presents an inexpensive instruction set extensions (ISE) of efficient cryptographic algorithms on 32-bit processors assuring various types of instruction (public/private key cryptography, random number generator (RNG) and secure hash function (SHF)). These extensions provide hardware instructions that implement a full algorithm in a single instruction. Our enhanced LEON2 SPARC V8 core with cryptographic ISE is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40-nm technology. The total area of the resulting chip is about 1.93 mm² and the estimated power consumption of the chip is 16.3 mW at 10 MHz. Hardware cost and power consumption evaluation are provided for different clock frequencies and the achieved results show that our circuit is able to be arranged in many security constrained devices.

In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented, in which short circuit current is controlled. Switching activity is decreased to reduce the consumed power of the scan flip-flop. Also, the total number of transistors through the path from input to the output is reduced and so the delay of the proposed scan flip-flop is decreased. Simulation results show 12% and 29% reduction in power consumption and delay of the proposed scan flip-flop, respectively. The results are given by comparison of our work with other scan flip-flops at 50% data switching activity.

This paper shows that a conventional semi-custom design-flow based on a energy efficient adiabatic logic (EEAL) cell library allows any VLSI designer to design and verify complex adiabatic arithmetic units in a simple way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom EEAL-based 32-bit carry-lookahead adder (CLA) has been designed in a TSMC 90-nm CMOS process technology and verified by CADENCE Design suite. Differential cascode voltage swing (DCVS) logic has been used to implement the newly proposed EEAL and it uses only a sinusoidal clock supply to ensure correct operation. Post-layout simulations show that semi-custom adiabatic arithmetic units can save significant amount of energy, as compared to the previously reported single clocked adiabatic logic and logically equivalent static CMOS implementation. Extensive CADENCE simulations have been done for the verification of the functionality of the proposed logic structure.

This paper proposes a method of buffering instructions by software-based prefetching. The method allows low-end processors to improve their instruction throughput with a minimum of additional logic and power consumption. Low-end embedded processors do not employ caches for mainly two reasons. The first reason is that the overhead of cache implementation in terms of energy and area is considerable. The second reason is that, because a cache's performance primarily depends on the number of hits, an increasing number of misses could cause a processor to remain in stall mode for a longer duration. As a result, a cache may become more of a liability than an advantage. In contrast, the benchmarked results for the proposed software-based prefetch buffering without a cache show a 5–10% improvement in execution time. They also show a 4% or more reduction in the energy-delay-square-product (ED²P) with a maximum reduction of 40%. The results additionally demonstrate that the performance and efficiency of the proposed architecture scales with the number of multicycle instructions. The benchmarked routines tested to arrive at these results are widely deployed components of embedded applications.