Journal of Circuits, Systems and Computers

Flash-based solid state drives (SSDs) have been widely used as storage medium because of their fast access speed, high reliability and low power consumption. In spite of these advantages, they inherit distinct characteristics such as no in-place updates, asymmetric operation speed and unit because they consist of NAND flash memories. Therefore, a disk-based hash index structure may result in severe performance degradation if it is directly deployed on a NAND flash memory-based storage system. In this paper, we propose a new hybrid hash index structure for flash-based SSDs. It delays and reduces the split operations which cause slow block erasure and additional read and write operations by exploiting overflow buckets according to the ratio of updates and deletions. Through various performance evaluations, we show the superiority of our proposed index structure by comparing it to other hash index structures for flash-based SSDs.

This paper presents the modeling of saturated dual stator induction generator (DSIG) for analysis of its transient and dynamic behavior for stand-alone operation. In the analytical model, the effect of common mutual leakage reactance between the two three-phase winding sets and the cross saturation have been considered. For this purpose, a detailed description of a procedure to introduce magnetic saturation in found models is presented. Paper also discusses the possibility of DSIG for supplying two individual loads by presenting the results of analytical and experimental study of transient behavior under various operating conditions. Use of such models leads to more accurate predictions in industrial drives, especially wind driven power generation systems. This is verified by experimental lab tests.

In this paper, three CNT-based full adder designs, called Design1, Design2 and Design3, are proposed. In these designs 12, 14 and 16 transistors are used, respectively. In all designs only 3-input NAND, Majority-not and NOR functions are used. First, a preliminary structure (Design1) is presented using 12 transistors. Then its weaknesses are tackled in two steps. In fact, in each step a new design is presented by adding two more transistors to its predecessor. Therefore two new structures called Design2 and Design3 are built in which Design3 is the most efficient one. To study the performance of Design3 versus other silicon-based and CNT-based 32-nm classical and state-of-the-art cells, comprehensive simulations with regard to various supplies, loads, operating frequencies, and temperatures are performed using Synopsys HSPICE tool. Simulation results confirm that the proposed cell is superior to the other cells. At last the robustness of Design3 against the diameter mismatches of CNTs which is one of the most important concerns of nanoelectronics is studied using Monte Carlo transient analysis. This simulation reveals that Design3 functions very well against manufacturing process variations.

This paper proposes a hybrid recurrent neuro-fuzzy (RNF) architecture for rotor speed regulation of indirect field oriented controlled (IFOC) induction motor (IM) drive. This approach incorporates Takagi–Sugeno–Kang (TSK) model-based fuzzy logic (FL) laws with a four-layer artificial neural networks (ANNs) scheme. Moreover, for the proposed RNF an improved self-tuning method is developed based on the IM theory and its high performance requirements. The principal task of the tuning method is to adjust the parameters of the FL in order to minimize the square of the error between actual and reference output. The convergence/divergence of the weights is discussed and investigated by simulation.

A mode-selectable oscillator (OSC) with variable duty cycle for improved charge pump efficiency is proposed in this paper. The novel OSC adjusts its duty cycle according to the operation mode of the charge pump, thus improves the charge-pump efficiency and dynamic performance. The control of variable duty cycle is implemented in digital logic hence it provides robust noise immunity and instantaneous response. The OSC and the charge-pump have been implemented in a 0.6-μm 40-V CMOS process. Experimental results show that the peak efficiency is 92.7% at 200-mA load, the recovery time is less than 25 μs and load transient is 15 mV under 500-mA load variation. The system is able to work under a wide range of input voltage (V_IN) in all modes with low EMI.

In this paper, an energy efficiency (EE) analysis for elastic optical networks (EONs) considering the adaptive allocation of the transmitted power, spectrum bandwidth, modulation format and forward error correction (FEC) type has been proposed. The trade-off between the FEC coding types and the optical layer EE (OL-EE) was investigated considering the capacity of information transmission and power consumption. The power consumption model considers elements involved in the lightpath establishment, namely transmitter, receiver, bandwidth-variable optical crossconnect (BV-OXC), optical amplifiers and network control. Numerical examples have demonstrated EE increasing for the lightpaths when adaptive FEC coding is deployed; furthermore, the EE varies with the distance of the optical network nodes and hop count. In this sense, it is observed that the EE decreases with the increasing of FEC energy per bit consumption; however, an operation region is verified in which the overall EE network with FEC is superior to the system without FEC coding. After this point, the increases in the FEC energy per bit consumption will affect negatively the EE metric. For instance, with the proposed OL-EE model it is possible to determinate the maximum energy consumption allowed to the FEC codes without OL-EE system degradation.

This work describes an ultra low voltage, low power and self biased comparator with wide input common-mode range. The proposed comparator consists of a preamplifier followed by a regenerative back-to-back inverter latch, where two push pull NMOS and PMOS pairs are exploited to bias the preamplifier and adjust its output common mode voltage. This leads to a wide input common mode voltage range (from 0 V to 390 mV). Furthermore, the operation of proposed structure is relatively insensitive to process and temperature variations due to the push pull transistors, and low power consumption is achieved through sub-threshold region operation. The comparator circuit is designed using 65-nm CMOS technology with minimum supply voltage of 0.4 V. Simulation results show an average power consumption ranging from 141 nW to 188 nW for different input common mode voltage levels, where a simple power gating technique is employed to further reduce the power consumption. The Monte Carlo simulation shows an average offset of 450 μV with standard deviation of 3.3 mV. In addition, the comparator shows a kickback noise range of 0.3–2.4 mV (with input common mode range from 0 V to 390 mV) and input referred noise of 0.9 mV. The proposed comparator operates up to clock frequency of 1 MHz in most process corners and temperature range of 0–100°C which is suitable for most of the biomedical sensing applications.

This study investigates a novel approach for pipeline time-to-digital converters (TDCs) which employs analog interpolation and time stretching techniques for digitizing the time interval between two input signals as well as increasing resolution. In the proposed converter, analog interpolation is performed based on a triple-slope conversion. This converter will be a 9-bit pipeline TDC which contains three time stretching amplifiers (TSAs) and four 2.5-b/stage TDCs. This converter does not use delay lines in its structure. It features low circuit complexity, low sensitivity to temperature, power supply and process (PVT) variations and high accuracy compared with the TDCs which have previously been proposed. Also, the time resolution, the dynamic range and the linear range of the TDC are improved. The proposed structure reduces the active chip area, the power consumption and the figure of merit (FoM). In addition, the integral nonlinearity (INL) and the differential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the TDC is designed in TSMC 45-nm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC.

When signum operation is applied in chaotic systems to realize piecewise-linearity, the original nonlinearity turns to be a kind of Boolean calculation, and correspondingly the chaotic circuit can be implemented by an analog structure embedded with some logic-gate circuits. In this paper, as examples based on the diffusionless Lorenz system we proposed a couple of chaotic flows with signum piecewise-linearity, which experimentally resorts to digital gate circuits. The experimental chaotic circuit with logic elements was built, and the oscillation in the physical circuit agrees well with the numerical simulation.

A routing aggregation (RA) is proposed for load balancing network-on-chip (NoC). The computing nodes with dense traffic and long distance in network are gathered into the same routing node to form a super router. A load balancing routing algorithm for super router is presented to improve the overall performance of NoC. A simulation platform using System C is presented to confirm the feasibility of the proposed design in 2D mesh. The simulation results show that the proposed RA design can reduce the average packet latency and the standard deviation of host link utilization 8% and 33%, respectively compared with the reported routing methods. The area cost and power consumption compared with the reported schemes are 22% and 12% less, respectively.

Recently, flash memory is widely used as a non-volatile storage for embedded applications such as smart phones, MP3 players, digital cameras and so on. The software layer called flash translation layer (FTL) becomes more important since it is a key factor in the overall flash memory system performance. Many researchers have proposed FTL algorithms for small block flash memory in which the size of a physical page of flash memory is equivalent to the size of a data sector of the file system. However, major flash vendors have now produced large block flash memory in which the size of a physical page is larger than the file system's data sector size. Since large block flash memory has new features, designing FTL algorithms specialized to large block flash memory is a challenging issue. In this paper, we provide an efficient FTL named LSTAFF* for large block flash memory. LSTAFF* is designed to achieve better performance by using characteristics of large block flash memory and to provide safety by abiding by restrictions of large block flash memory. Experimental results show that LSTAFF* outperforms existing algorithms on a large block flash memory.

Present study deals with the development of an artificial neural network (ANN)-based technique for tea quality quantification by monitoring fermentation and drying condition of the tea processing stages. An RS485 network-based instrumentation system has been developed and implemented for data collection for these two stages. Three calibrated sensor nodes are installed in the fermentation room due to its larger floor area to collect temperature and relative humidity (RH). Dryer inlet temperature is recorded using a calibrated thermocouple-based sensor node. From seven input parameters and target quality data obtained from tea taster, the ANN model has been developed to find the correlation between the process condition and the tea quality. From the correlation study, more than 90% classification rate is obtained from the model. The model is also validated with some independent data showing more than 60% correlation. Error in terms of root mean square error (RMSE) is about 0.17. This model will be helpful for improvement of tea quality.

Over time, more and more systems are becoming mixed-criticality systems. As the complexity and size of these systems grow, computation/communication resources should be more efficient than with traditional systems. Time-triggered (TT) Ethernet is a communication infrastructure that enables the use of a single physical communication infrastructure for distributed mixed-criticality applications while providing timely determinism. TTEthernet distinguishes between two traffic categories: The standard event-triggered (ET) traffic and the TT traffic. The latter, for which higher priority is granted, is subject to strong timing guarantees because of strict-periodicity constraint which fixes start-time cycles of TT messages. In addition, messages in an ET Ethernet traffic, which are of lower priority, have a minimum time interval between their transmission. The focus of this paper is on the timing analysis of a TTEthernet traffic by proposing: (i) A feasibility condition allowing to assess the timing requirements of TT messages. (ii) A schedulability condition allowing to check the schedulability of ET messages by taking into account of TT messages scheduling and idle times.

In recent days, network-on-chip (NoC) researchers focus mainly on the area reduction and low power consumption both in architectural and algorithmic approach. To achieve low power and high performance in NoC architecture, sense amplifiers (SAs) introduced which can consume less power under various traffic conditions. In order to analyze the performance of architectural NoC design before fabrication level, the new simulator is developed based on multi core processor with improved sense amplifier (MCPSA) in this work. The MCPSA simulator provides user, the flexibility of incorporating various traffic configurations and routing algorithm with user reconfigurable option. In addition, the different SA model can be put into the simulation in plug and play manner for evaluation. The NoC case studies are presented to demonstrate the NoC architecture with double tail sense amplifier (DTSA) and modified-DTSA (M-DTSA) design. The performance metric such as delay, data rate and power consumption is evaluated. The main idea of this new simulator is to interface multisim environment (MSE) into a NoC environment for validating any DTSA.

This paper introduces new fundamentals of the 2 × n RLC circuit network in the fractional-order domain. First, we derive the three general formulae of the equivalent impedances of the circuit network by using the matrix transform methods and constructing the differential equation models in three different cases. Moreover, we systematically study the effects of the system parameters on the impedence characteristics in the three different cases. Specifically, the new phenomena and laws are presented by the results of the numerical simulations, which are impossible in the conventional cases. Finally, a comparative sensitivity analysis about the three cases with respect to the fractional orders for the fractional-order circuit network is carried out in detail. Mathematical analyses and numerical simulations are included to validate the study.

This paper proposes a dual-mode controlled pulse width monostable multivibrator used for analogue signal processing applications that employs two differential voltage current conveyors (DVCCs), four passive components and an analogue switch. Unlike the traditional operational-amplifier-based monostable multivibrators, the proposed circuit contributes a dual-mode controlled scheme for adjusting the output pulse width through a voltage source and a grounded resistor. This paper discusses several previous designs and presents the circuit operations, related governing formulas, non-ideal effect problems, design considerations, and experimental examples of the proposed circuit. A prototype circuit was implemented, and commercially integrated circuits and discrete passive components were used to execute the experimental tests. The features of the proposed circuit are discussed, and the experimental results indicated that the circuit is feasibly used in dual-mode controlled pulse width for the output pulse and were consistent with those of the theoretical analyses.

A novel chaotic oscillator based on "cross-coupled" inverter rings is presented. The oscillator consists of a 3-ring to which higher odd n-rings are progressively coupled via diodes and pass gates; it does not contain reactive or resistive elements, and is thus suitable for area-efficient implementation on a CMOS integrated circuit. Numerical simulation based on piece-wise linear approximation predicted the generation of positive spikes having approximately constant periodicity but highly variable cycle amplitude. Simulation Program with Integrated Circuit Emphasis (SPICE) simulations and experimental data from a prototype realized on 0.7 μm technology confirmed this finding, and demonstrated increasing correlation dimension (D₂) as 5-, 7- and 9-rings were progressively coupled to the 3-ring. Experimental data from a ring of 24 such oscillator cells showed phase synchronization and partial amplitude synchronization (formation of small clusters), emerging depending on DC gate voltage applied at NMOS transistors implementing diffusive coupling between neighboring cells. Thanks to its small area, simple synchronizability and digital controllability, the proposed circuit enables experimental investigation of dynamical complexity in large networks of coupled chaotic oscillators, and may additionally be suitable for applications such as broadband signal and random number generation.