Journal of Circuits, Systems and Computers

The paper proposes hierarchical scheduling optimization scheme in hybrid cloud. Our proposed hierarchical scheduling takes advantage of the interaction of cloud users, private cloud and public cloud. For high level optimization in hybrid cloud, the objective of public cloud provider optimization is to maximize the revenue of providing virtual machines (VMs) and minimize the energy cost. The private cloud users' applications give the unique optimal payment to public cloud providers under deadline and cost constraint to maximize the satisfaction of private cloud user applications. The objective of low-level scheduling optimization is to minimize the cost and execution time of private cloud application. From the simulation results, the revenue, execution success ratio and resource utilization of our proposed hierarchical scheduling algorithm are better than other related works.

The reconfigurable mesh (R-Mesh) was shown to be a very powerful model capable of extremely fast solutions to many problems. R-Mesh has a wide range of applications such as arithmetic problems, image processing and robotics. The 2D R-Mesh was shown to be able to solve the path planning problem very fast.

In this paper, we propose an algorithm to compute a collision-free path, P, between a source and a destination in an environment with the existence of obstacles. Independent of the number of obstacles, k, the proposed algorithm runs in constant time and requires O(log²N) pre-processing time where N is the size of the R-Mesh. This is in contrast to the previous work that requires O(k) time with the same pre-processing time. We then consider the quality of the generated path. We present a constant-time modification to enhance the length of the path and analyze the generated path P in terms of the number of bends in P. We derive the number of bends in P for any set of obstacles. We also derive a necessary condition for the minimum number of bends in the path P, i.e., a lower bound on the number of bends. We finally identify a class of obstacles for which the above necessary condition is sufficient as well (tight bound).

Hot data identification in flash memory is of great interest because it significantly affects the garbage collection and wear-leveling performance. Presently, certain hot and cold data classification schemes based on Bloom filters (BFs) have been proposed. Although BFs are efficient in most cases, there is a significant trade-off between false positive rates, which are the result of hash value collisions and memory utilization. In this paper, we suggest a better data categorization mechanism that is based on a hashing technique called Fingerprinting by Random Polynomials with the aim of reducing false positive rates and achieving lower memory consumption compared to the BF-based schemes. We also introduce a new methodology for classifying write requests by linking the definition of hot and cold write requests to the flash memory software layer, the flash translation layer (FTL) characteristics. Our approach improves space utilization by representing each logical block number (lbn) by one counter in the hash table, and achieves an extremely low error rate by choosing the degree of the hash function based on the address space of the flash memory. In addition, we achieved lower false identification rates. We demonstrate the performance using mathematical analysis and trace-driven simulation.

This paper proposes a simultaneous multithreaded matrix processor (SMMP) to improve the performance of data-parallel applications by exploiting instruction-level parallelism (ILP) data-level parallelism (DLP) and thread-level parallelism (TLP). In SMMP, the well-known five-stage pipeline (baseline scalar processor) is extended to execute multi-scalar/vector/matrix instructions on unified parallel execution datapaths. SMMP can issue four scalar instructions from two threads each cycle or four vector/matrix operations from one thread, where the execution of vector/matrix instructions in threads is done in round-robin fashion. Moreover, this paper presents the implementation of our proposed SMMP using VHDL targeting FPGA Virtex-6. In addition, the performance of SMMP is evaluated on some kernels from the basic linear algebra subprograms (BLAS). Our results show that, the hardware complexity of SMMP is 5.68 times higher than the baseline scalar processor. However, speedups of 4.9, 6.09, 6.98, 8.2, 8.25, 8.72, 9.36, 11.84 and 21.57 are achieved on BLAS kernels of applying Givens rotation, scalar times vector plus another, vector addition, vector scaling, setting up Givens rotation, dot-product, matrix–vector multiplication, Euclidean length, and matrix–matrix multiplications, respectively. The average speedup over the baseline is 9.55 and the average speedup over complexity is 1.68. Comparing with Xilinx MicroBlaze, the complexity of SMMP is 6.36 times higher, however, its speedup ranges from 6.87 to 12.07 on vector/matrix kernels, which is 9.46 in average.

During the last few years, hardware Trojan horses (HTHs) have become one of the most important threats to the security of very large scale integrated (VLSI) chips. Many efforts have been made to facilitate the process of HTH detection, mostly based on the power analysis of chips. The techniques would be more beneficial if trust-driven techniques are used during the system design. Whereas design for hardware trust (DFHT) is one of the fields of interest, most current approaches include ad-hoc and gate-level design techniques. This paper discusses the advantage of physical-level design approaches with integrated strategies for improving the HTH-detection probability. As a proof of concept, a placement technique is presented with the goal of enhancing the ability of HTH detection techniques based on local power signal analysis. Our results show that the background effects on power pads can be leveraged by a simple partitioning-based placement algorithm. Minimizing the background effects leads to a better Trojan-to-background-effect ratio and more (by about 1.7 times) Trojan detectability.

The work presented in this paper is concerned with the designing of a variable fractional delay (VFD) FIR filter using least square method encompassing all delay values p. First, the frequency response, e^-jωp, of the VFD filter is approximated using power series expansion of an exponential function and then, it is represented in terms of frequency response of the differentiator. Next, the proposed least square method adopts a novel cost function which includes all the fractional delay values. Finally, design and application examples are given to illustrate that the proposed least square method have better design accuracy and significantly reduction in magnitude error with the same degree of complexity than existing least square methods.

This paper analyzes the cell edge mobile user performance in the downlink cellular system. We develop frame-work for coverage probability and spectral efficiency. In particular, we analyzed the performance of multi-antenna mobile users under multi-antenna base stations (BSs). The expressions of coverage probability and spectral efficiency are derived for cell edge user using stochastic geometry. We investigate how much the performance of cell edge user is improved when distances connecting BSs and cell edge users are modeled with cell edge null probability distribution. The probability of coverage and spectral efficiency is studied using zero-forcing beam-forming and the performance metrics are compared between coordinated scheduling (CS) and without coordinated scheduling (w/o CS). The interesting observation from our results is that the edge user coverage and rate is closely approaching towards the inner cell typical mobile user's rate and coverage, and the performance is verified with relative probability of coverage gain analysis.

In a big data era, there are and will be more demands and higher requirements for data organization and management in the storage system. Previous studies on semantic relations of blocks have set an essential theoretical basis in storage systems. Revealing semantic relationship of blocks has great scientific values and indicates a promising prospect in the application. However, only qualitative description of block correlations has been obtained by traditional ways, and few researches have been done on unifying and quantizing the blocks semantic relationships.

In this paper, an uniform design-aided gene expression programming (UGEP) method has been proposed to address this issue. After analyzing historical access streams, a quantitative description system on semantic relationship of blocks is established. The semantic relationship of blocks can also be used in prefetching in storage system, which means the next access block can be calculated by the prefetching model. Simulation tests in four real system traces indicate that compared with sequential prefetching and no prefetching model, the quantitative semantic relationships model based on UGEP can highly improve the performance of the storage system. The experimental results show that in Cello-92 cases, compared with no prefetching method and sequential prefetching method, prefetching based on UGEP can reduce average I/O response time by 23.7% and 17.9%, and hit ratio is also increased by 16% and 8% as well.

This paper presents a technique towards obtaining an estimate of the value of inductor(s) to expand the bandwidth of operation in a complementary metal-oxide semiconductor (CMOS) amplifier system which exploits shunt peaking principle. The basic principle is placement of the zeros of the transfer function in an interleaved manner relative to the uncompensated RC time-constant frequency (TCF) and the band-edge frequency (BEF) (i.e., product of the poles) of the transfer function. Application of the analytical results has been demonstrated for (i) a common-gate (CG) amplifier stage in a 0.18-μm CMOS process and (ii) an inter-stage inductor coupling network which serves as an interface between two amplifier stages. MATLAB simulation has been used to obtain the range of design inductance values. The TSMC 180-nm CMOS process has been used in Cadence CAD environment to validate the theoretical predictions. The inductors laid out have been modeled using the ASITIC program to obtain more realistic results. The proposed technique provides a bandwidth extension of the CMOS common-gate amplifier from 6.68 GHz to 10.4 GHz with 1 dB peaking using only a 1.85-nH inductor. For the inter-stage coupling network, the suggested design procedure leads to a bandwidth extension ratio (BWER) exceeding three, with less than 3-dB ripple.

The lifetime of battery operated sensor nodes is a critical issue. In the case of event driven applications where events take place infrequently, most of the energy is wasted in idle listening by the sensor nodes. The sensor node in continuous idle listening mode drains the batteries approximately in two days. This paper describes a passive wake-up circuit (PWUC), designed for 2.45 GHz ISM band, to suppress the idle listening by waking-up the sensor nodes asynchronously. The proposed PWUC consists of receiving antenna, RF rectifier and matching network. The impedance and number of stages of the RF rectifier have been optimized to yield the maximum sensitivity and conversion efficiency. The lumped component based external matching network has also been proposed to boost-up the received input voltage through antenna. The purpose behind the use of external matching network is to reduce the fabrication cost of RF rectifier. Very few realizations of passive wake-up circuits are reported in the literature and none of them presents the sensitivity and global conversion efficiency above -11 dBm and 30–40%, respectively. The designed PWUC gives an output voltage of 1.8 V for a -23 dBm received RF power and a 1 MΩ load, which translates to 69% global power conversion efficiency (GPCE). RF rectifier is designed in UMC 180-nm 1P6M CMOS standard process.

Because ternary computer has more superiority than other d-ary number systems, we focus on the investigation of ternary elementary quantum gates and the synthesis algorithm of ternary quantum logic circuits. Above all, Pauli operators and their matrices on qutrit are introduced. Then eight qutrit operators are selected as elementary operators and eight qutrit quantum logic gates are defined. Permutation groups are introduced to characterize the quantum gates and quantum logic circuits. Some important qutrit quantum logic gates are defined also, such as QNOT, QKCXi, EQKCXi, QSwap, QCNOT and EQCNOT. Based on these elementary gates, we prove two very important theorems: (1) all qutrit quantum reversible logic circuit can be generated by Xi gate and QKCXi gate; (2) all qutrit quantum reversible logic circuits can be generated by Xi gate and QCNOT gate. The two theorems indicate that any complicated qutrit quantum reversible circuit can be constructed by the simplest ternary quantum gate. This will greatly simplify the implementation difficulty of quantum circuit. Subsequently, we propose a synthesis algorithm for qutrit quantum reversible logic circuit, which is verified through simulation experiment by the computer program we have designed.

Elliptic curve cryptosystems (ECC) are becoming more and more popular and are included in many standards, as they offer high security strength when compared with other conventional public-key cryptosystems, for the same key length. But the security strength of hardware implementations of ECC is challenged by side channel attacks (SCA) such as power analysis. Reversible logic circuits ideally consume zero energy, which serves as the motivation to implement cryptographic algorithms against power analysis attacks. This paper proposes two new hardware architectures for performing montgomery multiplication in GF(p) and GF(2^m), as they are the power consuming operations in ECC. The two architectures are optimized to reduce the hardware cost and they are then implemented in reversible logic with reduced number of quantum cost. In this work, the reversible logic synthesis is performed with Toffoli family of reversible gates. The performance metrics of all the multipliers are analyzed and properly tabulated. Scalar multiplication on elliptic curve points, which is the core operation used in every elliptic curve cryptosystem, has been implemented in reversible logic by using the proposed reversible montgomery multipliers.

Electric load forecasting is increasingly important for the industry. This study addresses the load forecasting based on the discrete Fourier transform (DFT) interpolation. As the most common analysis method in the frequency domain, the conventional Fourier analysis cannot be directly applied to prediction. From the perspective of time-series analysis, electric load movement influenced by various factors is also a time-series, which is usually subject to cyclical variations. Then with periodic extension for the load movement, a forecasting approach based on the DFT interpolation is proposed for predicting its movement. The proposed DFT interpolation prediction model is applied to experiments of forecasting the daily EUNITE load movement and annual load movement of State Grid Corporation in China. The experimental results and analysis show potentiality of the proposed method. Performance comparisons indicate that the proposed DFT interpolation model performs better than the three commonly used interpolation algorithms as well as the classical autoregressive (AR) model, the ARMA model, and the BP-artificial neural network (ANN) model on the same forecasting tasks.

This paper presents a new high-performance and low-power single-supply voltage level converter (SSLC) and a new carry save array multiplier based on clustered-voltage scaling (CVS) technique for ultra-low-power applications. The multiplier operates with low and high supply voltage (V_DDL, V_DDH) and at its end stage, the proposed low-power SSLC is utilized to prevent static power dissipation at the next stage working with V_DDH and to enhance the output driving capability. In the proposed SSLC, dynamically-controlled source-body voltage, reduced drain induced barrier lowering (DIBL) effect and diode-connected transistor with body-biasing have been utilized properly in order to reduce the power consumption significantly without considerable speed degradation. The results of the simulations conducted using Cadence with standard 90-nm CMOS technology demonstrate the superiority of the proposed multiplier utilizing the proposed LC in terms of static and total power consumptions as well as power-delay product (PDP) as compared to the multipliers utilizing the previous level converters (LCs) and the single supply multiplier. It is worth mentioning that the static power, total power and PDP of the proposed low-power multiplier are on average 75%, 73% and 16%, respectively lower than the single-supply multiplier.

This work presents a bandgap voltage reference (BGR) integrated in 0.25-μm bipolar-CMOS-DMOS (BCD) technology. The BGR circuit generates a reference voltage of 1.22 V. It is able to withstand large supply voltage variations of vehicle applications from 4.5 V, e.g., in case of cranking, up to 60-V, maximum value in case of emerging 48-V battery systems for hybrid and electrical vehicles. The circuit has an embedded high-voltage (HV) pseudo-regulator block that provides a more stable internal supply rail for a cascaded low-voltage bandgap core. HV MOS are used only in the pre-regulator block thus allowing the design of a BGR with compact size. The proposed architecture permits to withstand large input voltage variations with a temperature drift of a hundred of ppm/°C, a line regulation (LR) of few mV/V versus the external supply voltage and a power supply rejection ratio (PSRR) higher than 90 dB.

Mapping constitutes a very important step in network-on-chip (NoC)-based implementation of an application. An application is often represented in the form of an application core graph. The cores of the core graph communicate between themselves using the underlying network. This paper presents a constructive heuristic to statically map applications on two-dimensional mesh-connected NoC. The approach corresponds to a design time decision of attachment of cores to the routers. The mapping results, in terms of overall communication cost metric, have been compared with many well-known techniques reported in the literature and also with an exact method built around integer linear programming (ILP). A thorough complexity analysis of the algorithm has been performed. For smaller benchmarks, the results obtained are same as those for the ILP generated solutions. For benchmarks containing 64 and higher number of cores, the mapping solutions are better than the existing ones. Dynamic performances of the mapped solutions have been compared with respect to synthetically generated self-similar traffic. In many cases, our approach requires less latency and energy per packet than the existing methods while providing higher throughput.

Microstrip Wilkinson power dividers with harmonic suppression and size reduction are investigated. It is found that by loading reactive components at the middle of high impedance transmission lines (TLs), both size reduction and harmonic suppression can be achieved. Analyses and designs of such a kind of power divider are formulated in this paper. To demonstrate the design methodology, two power dividers centered at 1.8 GHz are optimally designed and confirmed by experiments. As compared with conventional Wilkinson power divider, the proposed power divider exhibits 55.6% size reduction, and high suppressions are achieved for 2nd and 3rd harmonic components. Both simulations and measurements are presented with good agreement.