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A Low-Power Edge Detection Technique for Sensor Wake-Up Applications

Center for RFIC and System Technology, School of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu 611731, P. R. China

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Haibo Wang

Department of Electrical and Computer Engineering, Southern Illinois University, Carbondale, Illinois 62901, USA

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, and

Guangjun Wen

Center for RFIC and System Technology, School of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu 611731, P. R. China

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https://doi.org/10.1142/S0218126615501571Cited by:4 (Source: Crossref)

Abstract

A novel low-power edge detection circuit is presented in this work. Upon the arrival of signal falling edge, the proposed design establishes a small voltage difference between the gate and source terminals of a MOS transistor which slightly increases the MOS transistor leakage current. A current integration-based approach is used to robustly sense the current change and subsequently detect the signal falling edge. The design is suitable for ultra-low-power sensor wake-up circuits. Design guidelines for achieving optimal detection sensitivity as well as the implementation of calibration circuits for coping with process variations and mismatches are discussed in the paper. Simulation results are presented to demonstrate the performance of the proposed circuit.

This paper was recommended by Regional Editor Piero Malcovati.

Keywords:

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