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This paper presents a low-power fourth-order single-bit switched capacitor sigma-delta modulator implemented by 180nm CMOS technology. In the modulator, the Floating Inverter Amplifier (FIA) with Correlated Level Shift (CLS) technique increasing gain is employed to decrease the modulators power consumption, and a two-tap Finite Impulse Response (FIR) is used in a feedback loop to reduce the integrator output swings. With the help of a simple digital circuit, the mismatches influence on the first-order integrators capacitor is mitigated because of reusing the sampling capacitor. Additionally, the work exploits the charge-sharing module to reduce the integrating capacitors size. The proposed modulator achieves 97.8dB peak Signal-to-Noise and Distortion Ratio (SNDR) at 102.4kHz over a bandwidth of 400Hz under the supply voltage of 1.2V VDD and 1.2V reference voltage while consuming a total power consumption of 3.94$\mu$W.

In this paper, a logic style that is becoming increasingly popular is presented, which is called MOS Current Mode Logic (MCML). MCML is a novel and useful logic style for high-speed, low-power and mixed-signal applications. Its high-speed switching, low supply voltage and reduced output voltage swing contribute to its high performance, low power dissipation, and low noise features. MCML circuits are compared to several other logic styles, such as conventional static CMOS, dynamic logic, and traditional emitter coupled logic (ECL) in terms of power, delay and common mode noise immunity. MCML circuits seem to be very promising in high-speed, low-power and mixed-signal digital circuit applications, such as portable electronic devices, gigahertz microprocessors, and optical transceivers.

Implantable biomedical sensors and continuous real time in vivo monitoring of various physiological parameters requires low-power sensor electronics and wireless telemetry for transmission of sensor data. In this article, generic blocks required for such systems have been demonstrated with design examples. Ideally neural or electro-chemical sensor signal monitoring units comprise of low noise amplifiers, current or voltage mode analog to digital domain data conversion circuits and wireless telemetry circuits. The low-noise amplifier described here has a novel open loop amplifier scheme used for neural signal recording systems. The design has been implemented using 0.5-μm SOI-BiCMOS process. The fabricated chip can work with 1 V supply and consumes 805 nA. The current mode analog to digital conversion signal processing circuitry takes the current signal as an input and generates a pulse-width modulated data signal. The data signal is then modulated with a high frequency carrier signal to generate FSK data for wireless transmission. The design is fabricated in 0.5-μm standard CMOS process and consumes 1.1 mW of power with 3.5 V supply.

A low-power and low-data-rate (100 kbps) fully integrated CMOS impulse radio ultra-wideband (IR-UWB) transmitter for biomedical application is presented in this paper. The transmitter is designed using a standard 180-nm CMOS technology that operates at the 3.1-5 GHz frequency range with more than 500 MHz of channel bandwidth. Modulation scheme of this transmitter is based on on-off keying (OOK) in which a short pulse represents binary “1” and absence of a pulse represents binary “0” transmission. During the ‘off’ state (sleep mode) the transmitter consumes only 0.4 μW of power for an operating voltage of 1.8 V while during the impulse transmission state it consumes a power of 36.29 μW. A pulse duration of about 3.5 ns and a peak amplitude of the frequency spectrum of about -47.8 dBm/MHz are obtained in the simulation result which fully complies with Federal Communication Commission (FCC) regulation.

Achieving high-gain and low-noise operation of bulk-driven (BD) operational transconductance amplifier (OTA) with low-power consumption is a challenging task owing to inherent low transconductance and high noise in BD MOSFET. In this paper, we report a self-cascode partial positive feedback (SCPPF) approach-based BD OTA and have fairly compared the results with regular single MOS partial positive feedback (PPF) approach-based BD OTA. In comparison to regular BD PPF OTA, the proposed BD SCPPF OTA yields an improved gain of 68.71 dB, gain-bandwidth of 39.4 kHz, power consumption of 630 nW, output impedance of 0.4 MΩ and common mode rejection ratio of 134.4 dB for same input referred noise of 1.11 μV/√ Hz at frequency of 10 Hz and supply voltage of ±0.5 V. The area consumed by BD SCPPF OTA is 0.0523 mm². The proposed BD SCPPF OTA can be possibly used to improve the performance of biomedical analog front-end sensing and signal processing systems.

In this paper, we propose a voltage scaling technique with multiple supply voltages for low-power designs. We adopt the path sensitization technique and release the clustering constraint used by the previous works. Our technique first operates the gates with the lowest feasible supply voltages and then uses an existing path selection algorithm for optimization. Experiments are conducted on all ISCAS85 benchmarks and the results show that significant power can be further reduced by our technique in comparison with the previous works. Furthermore, the results generated by our technique are close to the optimal values.

In many VLSI chips, the power dissipation of the clocking system that includes clock distribution network and flip-flops is often the largest portion of total chip power consumption. In the near future, this portion is likely to dominate total chip power consumption due to higher clock frequency and deeper pipeline design trend. Traditionally, two approaches have been used: (1) to reduce power consumption in the clock tree, several low-swing clock flip-flops and double-edge flip-flops have been introduced; (2) to reduce power consumption in flip-flops, conditional capture, clock-on-demand, data-transition look-ahead techniques have been developed. Recently, pulsed latch type flip-flops are introduced in several high-performance microprocessors to reduce E × D. In this paper, these flip-flops are described with their pros and cons. Then, a new circuit technique is described along with simulation results. The proposed pulsed latch reduces E × D by 82.6% to 95.4% compared to conventional flip-flops.

A novel logic family, called Split-Level Charge-Sharing Differential Logic (SCSDL), is proposed in this letter. The SCSDL uses the charge recycling technique to reduce power dissipation of differential logic in the precharge phase. The simulation results show that the SCSDL has the best power-delay product compared to several other differential logic families. An eight-bit carry lookahead adder (CLA) designed using the proposed SCSDL can reduce at least 30.64% of power-delay product compared to DCVSL CLA dissipation. A test chip was fabricated to illustrate the feasibility of the SCSDL circuit.

In this paper, we present an address bus coding method to reduce dynamic power dissipations and delay faults at on-chip applications. The purpose of the proposed new coding technique is to diminish the switching and coupling activities on instruction address busses effectively. The proposed bus coding method is called the exclusive-OR and bus inverter transition signaling (XOR–BITS) code. The XOR–BITS code has four advantages. Firstly, it can save a large number of switching activities. Secondly, it can also save a large number of coupling activities. Thirdly, its architecture belongs to a low-complexity architecture. Finally, its delay is short after optimizations. Experimental results show that the XOR–BITS coding indicates an average reduction in 78.5% switching activities and 21.9% coupling activities on instruction address busses. It surpasses the other address coding methods in total power dissipations when the load capacitance is more than 1 pF/bit with the TSMC 0.13 μm CMOS technology. For a 50 pF/bit load capacitance, it achieves a 74.9% average reduction in total power dissipations, compared with the un-coded schemes by using seven benchmarks. Similarly, our method also surpasses the other address bus coding methods with the TSMC 0.18 μm CMOS technology.

This work proposes and develops an original compensation approach for low-power three-stage operational transconductance amplifiers driving large capacitive loads. The proposed solution is based on the basic reversed nested Miller compensation and exploits a voltage buffer and two nulling resistors in the compensation network, along with a feedforward stage to improve slewing and settling performance. A well-defined design procedure using the loop gain phase margin as the main design parameter is also developed. SPECTRE simulations on a three-stage amplifier are carried out and are found to be in excellent agreement with the theoretical analysis, showing a significant improvement of the proposed approach over traditional compensation strategies in terms of small-signal and large-signal performance. Monte Carlo simulation results finally prove the proposed technique to be well-guarded against process parameter variations.

The present paper addresses an improved low-power high-speed buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output voltage of the input differential amplifier and outputs an additional current signal providing slew-rate enhancement at the output stage. Post-layout simulations show that the proposed buffer can drive a 1 nF column line load with 8.5 V/μs slew-rate and 0.8 μs settling time, while drawing only 8 μA static current from a 3 V power supply.

This paper presents a low-power 10-bit 200 MS/s pipelined ADC in a 90 nm CMOS technology with 1 V supply voltage. To decrease the power dissipation efficiently, a new architecture using a combination of two power reduction techniques named double-sampling and opamp-sharing has been used to reduce the power consumption significantly, without any degradation in the performance of the ADC. In addition, the stage scaling technique has been applied to the ADC efficiently, and two-stage class A/AB and class A amplifiers and dynamic comparators have been used in sample and hold and sub-ADCs. According to HSPICE simulation results, the 10-bit 200 MSample/s pipeline ADC with a 9.375 MHz, 1-V_P-P,diff input signal in a 90 nm CMOS process achieves a SNDR of 58.5 dB while consuming only 30.9 mW power from a 1 V supply voltage.

This paper presents two novel Floating Current Source (FCS)-based CMOS negative second generation current conveyor (CCII-) realizations suitable for very large scale implementation. The proposed realizations provide high voltage and current tracking accuracy, as well as large voltage and current transfer bandwidths. Simulation results show that the first proposed wide-band CCII- bandwidth is about 972 MHz. Targeting low-power dissipation, a second low-power version of the wide-band CCII- is proposed at the expense of lower bandwidth and accuracy. The proposed CCII- realizations are layout-friendly because they can be easily fabricated in a systematic modular layout fashion. In addition, a fair comparison is held between the proposed realizations and the only FCS-based CCII- realizations in the literature to show the strength of the proposed circuits. The proposed two CCII- realizations show excellent immunity to process variations and transistor mismatch. In addition, they are insensitive to the temperature variations. Finally, two common CCII- applications are presented.

With the increasing deployment of Wi-Fi devices in portable embedded systems, the low power design at system level has attracted considerable research attention in the recent past. In this paper, based on hardware features and software architecture of the embedded Wi-Fi devices, we focus on dynamic power management, dynamic frequency scaling, and their influences upon the system power and performance. We propose effective and realizable system power management solution and application modes under various application requirements, such as response, bandwidth, and speed. Experimental results show that the proposed solutions can achieve significant energy savings.

This paper presents a low-power CMOS receiving signal strength indicator (RSSI). The main architecture of the circuit adopts a six-stage limiting amplifier (LA) in a logarithmic-linear form, which shows a good performance in weak signal detection. The RSSI achieves high tolerance to process, voltage, and temperature (PVT) variations by utilizing the unique nature of branch currents in a transconductance amplifier. The power consumption is decreased by using the weak-inversion LAs. Full-waveform current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low power consumption. Measured results show that in the 1 kHz–50 MHz frequency range, the input dynamic range is wider than 70 dB within ±2 dB linearity error. The chip occupies an area of 0.7 mm² × 0.3 mm² using a 0.18-μm CMOS. It draws 1.3 mA from a 1.8 V supply.

With each CMOS technology generation, leakage energy consumption has been dramatically increasing and hence, managing leakage power consumption of large last-level caches (LLCs) has become a critical issue in modern processor design. In this paper, we present EnCache, a novel software-based technique which uses dynamic profiling-based cache reconfiguration for saving cache leakage energy. EnCache uses a simple hardware component called profiling cache, which dynamically predicts energy efficiency of an application for 32 possible cache configurations. Using these estimates, system software reconfigures the cache to the most energy efficient configuration. EnCache uses dynamic cache reconfiguration and hence, it does not require offline profiling or tuning the parameter for each application. Furthermore, EnCache optimizes directly for the overall memory subsystem (LLC and main memory) energy efficiency instead of the LLC energy efficiency alone. The experiments performed with an ×86-64 simulator and workloads from SPEC2006 suite confirm that EnCache provides larger energy saving than a conventional energy saving scheme. For single core and dual-core system configurations, the average savings in memory subsystem energy over a shared baseline configuration are 30.0% and 27.3%, respectively.

Microcontrollers represent unavoidable parts of state-of-the-art system-on-chips (SoCs) and they are widely embedded as IP blocks. This paper describes design steps and the application of available low-power techniques, to the design of a microcontroller IP core with 8051 instruction set, based on a prescribed standard cell libraries. Choice of the technology node and the cell library supplier is a design challenge that was considered and conclusions reached. The necessary steps of microcontroller design flow are presented which enable power reduction at several abstraction levels. An optimal microcontroller was designed to be embedded in various SoCs. The goal was to get energy-efficient microcontroller operation in applications which don't require intensive data processing. The impact of technology scaling on microcontroller energy efficiency is considered by comparison of the results obtained from implementations in three standard cell technologies. Moreover, power dissipation models are created which allow for microcontroller's power estimation in low throughput sensors networks applications.

A novel low-power edge detection circuit is presented in this work. Upon the arrival of signal falling edge, the proposed design establishes a small voltage difference between the gate and source terminals of a MOS transistor which slightly increases the MOS transistor leakage current. A current integration-based approach is used to robustly sense the current change and subsequently detect the signal falling edge. The design is suitable for ultra-low-power sensor wake-up circuits. Design guidelines for achieving optimal detection sensitivity as well as the implementation of calibration circuits for coping with process variations and mismatches are discussed in the paper. Simulation results are presented to demonstrate the performance of the proposed circuit.

In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented, in which short circuit current is controlled. Switching activity is decreased to reduce the consumed power of the scan flip-flop. Also, the total number of transistors through the path from input to the output is reduced and so the delay of the proposed scan flip-flop is decreased. Simulation results show 12% and 29% reduction in power consumption and delay of the proposed scan flip-flop, respectively. The results are given by comparison of our work with other scan flip-flops at 50% data switching activity.

A design flow using the $g_{\text{m}}$/$I_{\text{D}}$ methodology with the adaptive particle swarm optimization (PSO) algorithm is proposed for the modern analog circuit in this paper. For the advanced CMOS process, $g_{\text{m}}$/$I_{\text{D}}$ methodology is suitable to the long channel and short channel design in all transistor operation regions. Different from the classical PSO algorithm, the adaptive PSO algorithm features the better search efficiency and faster convergence speed over the global search. Two amplifiers were designed and implemented in a standard 0.11$\mu$m CMOS process using MATLAB and HSPICE. Using the thermal noise coefficient $\gamma$ and the corner frequency $f_{\text{corner}}$, this paper explored the noise design budget of low-power multistage amplifier in different saturation modes. Detailed optimization of the objective function and constraints are classified into the mono-objective case and the multi-objective case. The total running times of simulations are 5649 s and 6813 s while the errors are less than 9% and 10%, respectively. Compared with CODE, GA$+$PF and DE$+$PF algorithms, it can save more running time and improve the accuracy of the design. Moreover, it provides more design freedom for the trade-off among gain, the gain-bandwidth (GBW) product, noise and the phase margin under worst cases without extra tweaking. Not only can the methodology work in the 0.18$\mu$m CMOS process, but also be migrated to the 0.11$\mu$m CMOS process, even in the nanometer analog circuit.