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IMPROVED POWER-EFFICIENT RNMC TECHNIQUE WITH VOLTAGE BUFFER AND NULLING RESISTORS FOR LOW-POWER HIGH-LOAD THREE-STAGE AMPLIFIERS

DIEES (Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi), University of Catania, Viale A. Doria, 6 – I-95125 Catania, Italy

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GAETANO PALUMBO

DIEES (Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi), University of Catania, Viale A. Doria, 6 – I-95125 Catania, Italy

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SALVATORE PENNISI

DIEES (Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi), University of Catania, Viale A. Doria, 6 – I-95125 Catania, Italy

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https://doi.org/10.1142/S021812660900568XCited by:0 (Source: Crossref)

Abstract

This work proposes and develops an original compensation approach for low-power three-stage operational transconductance amplifiers driving large capacitive loads. The proposed solution is based on the basic reversed nested Miller compensation and exploits a voltage buffer and two nulling resistors in the compensation network, along with a feedforward stage to improve slewing and settling performance. A well-defined design procedure using the loop gain phase margin as the main design parameter is also developed. SPECTRE simulations on a three-stage amplifier are carried out and are found to be in excellent agreement with the theoretical analysis, showing a significant improvement of the proposed approach over traditional compensation strategies in terms of small-signal and large-signal performance. Monte Carlo simulation results finally prove the proposed technique to be well-guarded against process parameter variations.

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