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EFFECTS OF PARAMETER VARIATIONS ON TIMING CHARACTERISTICS OF CLOCKED REGISTERS

WILLIAM R. ROBERTS

TAC Corporation, One High Street, North Andover, MA 01845, USA

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and

DIMITRIOS VELENIS

Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York, 14627, USA

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https://doi.org/10.1142/S0218126609005678Cited by:0 (Source: Crossref)

Abstract

Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of parameter variations on the timing characteristics of registers that determine the timing constraints are investigated in this paper. The sensitivity of the setup time and data propagation delay to variations in power supply voltage, temperature, and gate oxide thickness is demonstrated for four different register designs. Furthermore, design modifications are proposed that enhance the robustness of each register to variation effects.

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