Journal of Circuits, Systems and Computers

In this paper, different model predictive control synthesis frameworks are examined for DC–DC quasi-resonant converters in order to achieve stability and desired performance. The performances of model predictive control strategies which make use of different forms of linearized models are compared. These linear models are ranging from a simple fixed model, linearized about a reference steady state to a weighted sum of different local models called multi model predictive control. A more complicated choice is represented by the extended dynamic matrix control in which the control input is determined based on the local linear model approximation of the system that is updated during each sampling interval, by making use of a nonlinear model. In this paper, by using and comparing these methods, a new control scheme for quasi-resonant converters is described. The proposed control strategy is applied to a typical half-wave zero-current switching QRC. Simulation results show an excellent transient response and a good tracking for a wide operating range and uncertainties in modeling.

Yield maximization is an important aspect in the design of integrated circuits. A prerequisite for its automation is a reliable and fast worst performance analysis which results in corners that can be used in the process of circuit optimization. We formulate the constrained optimization problem for finding the worst performance of an integrated circuit and develop a direct search method for solving it. The algorithm uses radial steps and rotations for enforcing the inequality constraint. We demonstrate the performance of the proposed algorithm on real world design examples of integrated circuits. The results indicate that the algorithm solves the worst performance problem in an efficient manner. The proposed algorithm was also successfully used in the process of yield maximization, resulting in a 99.65% yield.

In this paper a novel method for circuit analysis is proposed. It is based on using symbolic analysis in matrix form, which is especially appropriate for repetitive similar calculations of the same circuit. This method, which applies hyper-complex numbers (hypernions), was first developed by the authors for analyzing the non-sinusoidal operation of electrical circuits. Now, the method has been extended to the analysis of electronic/switching circuits in which the sources and/or the parameters are step-wisely changed as a result of switching. Such circuits are common in different kinds of DC-DC converters (such as Buck, Boost, Cuk, etc.). The proposed method gives a new approach to the analysis of the above circuits by opening the possibility of treating them in a general-analytical form, just like in regular electrical circuits having a constant configuration and constant parameters. The computation of such kinds of circuits by using the proposed method becomes very simple, since the circuit does not have to be analyzed many times, each time for a different configuration, but all at once by performing a parallel computation. The theoretical presentation is accompanied by numerical examples.

Contemporary memory system design aims to achieve high performance and low energy consumption at a reasonable cost. To balance these requirements, we propose a modular reconfigurable architecture to design memories over FPGAs. The proposed memory system can be reconfigured taking into account: the number of words, the word size of the data, the number of physical memory banks and the number of ports of the banks. Different operating modes have been defined, each one implying a certain configuration for the memory system. Simulations of these modes show the performance of our reconfigurable memory in terms of timing and power consumption.

With technology scaling, leakage power has become an important part of the total power consumption, affecting both yields and lifetime of digital circuits. Dual V_th assignment, which was an effective method to reduce leakage power in the past, is also effective in today's technologies with certain modifications. In this paper, based on our statistical timing analysis (SSTA) framework, we presented a dual V_th assignment method which can effectively reduce the leakage power even in the presence of large V_th variation. Besides, taking the correlation between gates into account, we propose a novel statistical DAG pruning method to speed up the dual V_th assignment algorithm. Experimental results show that statistical dual V_th assignment can reduce on average 95% and 40% more leakage current compared with the conventional static method, without affecting the performance constraints under 180 nm and 90 nm technology nodes. Also our statistical DAG pruning method can reduce 30% gates in the circuit on average and save up to 50% of the total runtime in the 90 nm technology node.

With higher operating frequencies, transmission lines are required to model global on-chip interconnects. In this paper, an accurate and efficient solution for the transient response at the far end of a transmission line based on a direct pole extraction of the system is proposed. Closed form expressions of the poles are developed for two special interconnect systems: an RC interconnect and an RLC interconnect with zero driver resistance. By performing a system conversion, the poles of an interconnect system with general circuit parameters are solved. The Newton–Raphson method is used to further improve the accuracy of the poles. Based on these poles, closed form expressions for the step and ramp response are determined. Higher accuracy can be obtained with additional pairs of poles. The computational complexity of the model is proportional to the number of pole pairs. With two pairs of poles, the average error of the 50% delay is 1% as compared with Spectre simulations. With ten pairs of poles, the average error of the 10%-to-90% rise time and the overshoots is 2% and 1.9%, respectively. Frequency dependent effects are also successfully included in the proposed method and excellent match is observed between the proposed model and Spectre simulations.

This paper presents different novel CMOS realizations for the differential difference operational floating amplifier (DDOFA). The DDOFA was first introduced in Ref. 1 and was used to realize different analog circuits like integrators, filters and variable gain amplifiers. New CMOS realizations for the DDOFA are introduced in this literature. Furthermore the DDOFA is modified to realize a fully differential current conveyor (FDCC). Novel CMOS realizations of the FDCC are presented. The FDCC is used to realize second-order band pass–low-pass filter. Performance comparisons between the different realizations of the DDOFA and FDCC are given in this literature. PSPICE simulations of the overall proposed circuits are given using 0.25 μm CMOS Technology from TMSC MOSIS model and dual supply voltages of ±1.5 V.

Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of parameter variations on the timing characteristics of registers that determine the timing constraints are investigated in this paper. The sensitivity of the setup time and data propagation delay to variations in power supply voltage, temperature, and gate oxide thickness is demonstrated for four different register designs. Furthermore, design modifications are proposed that enhance the robustness of each register to variation effects.

This work proposes and develops an original compensation approach for low-power three-stage operational transconductance amplifiers driving large capacitive loads. The proposed solution is based on the basic reversed nested Miller compensation and exploits a voltage buffer and two nulling resistors in the compensation network, along with a feedforward stage to improve slewing and settling performance. A well-defined design procedure using the loop gain phase margin as the main design parameter is also developed. SPECTRE simulations on a three-stage amplifier are carried out and are found to be in excellent agreement with the theoretical analysis, showing a significant improvement of the proposed approach over traditional compensation strategies in terms of small-signal and large-signal performance. Monte Carlo simulation results finally prove the proposed technique to be well-guarded against process parameter variations.

WLAN standards make use of different transmission modes to cope with different channel conditions, these modes make use of different modulation constellations and code rates. Data encoding is done with a 64-state convolutional code of rate 1/2, some modes employ this basic rate and others puncture the encoded data to obtain a rate of 3/4. At the receiver, the decision depth needed by the Viterbi decoder is higher for decoding punctured modes than for decoding non-punctured modes, this means that punctured modes need a greater area and, then, they cause a higher power consumption. This fact is used in this letter to reduce the power consumption of the Viterbi decoder when dealing with half-rate code modes, an architecture that disables the unnecessary hardware in the non-punctured modes allows a reduction of 20% in the dynamic power consumption with an area increase of only 1%.