Journal of Circuits, Systems and Computers

Two new types of floating current conveyors are introduced. Each type has four ports: Y, X and two Z ports. The first type is the Floating Second Generation Current Conveyor (FCCII) and includes both CCII+ and CCII- as special cases. The second type is the Floating Inverting Second Generation Current Conveyor (FICCII) and includes both ICCII+ and ICCII- as special cases. The Nodal Admittance Matrix (NAM) stamp for the Nullator-Pathological Current Mirror is derived. Examples are given together with a CMOS circuit realizing both the FCCII and FICCII.

The Differential Voltage Current Conveyor (DVCC) with its two polarities namely DVCC- and DVCC+ are reviewed together with their pathological element representations. Their two adjoint building blocks are the Balanced Output Current Conveyor (BOCCII) and the Balanced Output Inverting Current Conveyor (BOICCII) are also discussed with their pathological element representations. The universal CMOS circuit realizing these four building blocks is also included. The Nodal Admittance Matrix (NAM) stamp for the DVCC-, DVCC+, BOCCII and BOICCII are also given. Among the four basic building blocks considered the DVCC- is the only floating building block. Examples are given showing that some of the reported filters are related to each other by the adjoint network theorem.

This paper, according to the best of our knowledge, provides the very first solution to the hardware implementation of the complete decision tree inference algorithm. Evolving decision trees in hardware is motivated by a significant improvement in the evolution time compared to the time needed for software evolution and efficient use of decision trees in various embedded applications (robotic navigation systems, image processing systems, etc.), where run-time adaptive learning is of particular interest. Several architectures for the hardware evolution of single oblique or nonlinear decision trees and ensembles comprised from oblique or nonlinear decision trees are presented. Proposed architectures are suitable for the implementation using both Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Results of experiments obtained using 29 datasets from the standard UCI Machine Learning Repository database suggest that the FPGA implementations offer significant improvement in inference time when compared with the traditional software implementations. In the case of single decision tree evolution, FPGA implementation of H_DTS2 architecture has on average 26 times shorter inference time when compared to the software implementation, whereas FPGA implementation of H_DTE2 architecture has on average 693 times shorter inference time than the software implementation.

This paper offers a new approach to analyses of cycloconverter operation. The difference equations describing the cycloconverters' transient and steady-state operating regimes are derived. Theoretical predictions were validated by a computer program which calculated the load current of different cycloconverter topologies using the proposed methodology. The calculated and experimental results are compared and found to be in good agreement.

In this paper, we investigate the multiple input multiple output (MIMO) direct sequence bipolar pulse amplitude modulation (DS-BPAM) ultra wideband (UWB) system over indoor multipath fading channels based on the research of Alamouti space-time block codes (STBC) and DS-BPAM UWB system. Selective Rake (SRake) receiver is employed in this paper in order to deal with the multipath effects. Theoretical bit error probability of the MIMO DS-BPAM UWB system with SRake receiver is derived. Simulation results of the MIMO DS-BPAM UWB system with SRake receiver and conventional coherent receiver over multipath fading channels are provided. The results show the efficiency of the MIMO DS-BPAM UWB system with SRake receiver.

This paper explores a family of augmented FIFO replacement policies for highly setassociative caches that are common in low-power embedded processors. In such processors, the implementation cost and complexity of the replacement policy is as important as the cache hit rate. By exploiting the cache hit way information between two replacements, the proposed replacement schemes reduce cache misses by 1% to 18% on average depending on the cache configuration, compared with the conventional FIFO policy. The proposed schemes come at a small implementation cost of additional state bits and control logic. The reduction in cache misses directly translates into data access energy savings of 1% to 15% on average, depending on the cache configuration. Our work suggests that there is room for improving the popular FIFO policy at a small cost.

Storage components are a major source of energy dissipation in modern superscalar microprocessors. As the instruction windows get larger with each generation of processors, register files and other structures that hold intermediate data become larger and dissipate more power. Therefore it is important to find new ways to reduce the energy dissipation of data holding components. Many values written to and read from these storage components are known to require fewer bits than is provided by the storage space. Upper order bits of these values are unnecessary and energy savings can be achieved by not writing and reading these bits. Floating value data has different characteristics and offer special energy savings opportunities. In this paper we analyze the bit-level statistics of data values and propose simple modifications to data holding components that save significant energy inside the processors. Our results show that by using simple modifications on the storage components it is possible to achieve 40% reduction in the integer register file energy dissipation and up to 60% reduction in the immediate field of the issue queue. We also show that energy dissipation can be reduced by half for some floating point benchmarks by identifying values that indicate a zero operand.

This paper presents a novel low-voltage single stage CMOS RF Variable Gain Amplifier (RFVGA) designed in 130 nm IBM CMOS process technology using current feed-back gain-independent impedance matching. The proposed RFVGA has a nearly constant gain over the 400 MHz–1 GHz frequency band. Also, it has a 70 dB gain variation (-40 dB to 30 dB) which is decibel-linear within this frequency band for a control voltage in the range of 0.41 V–0.81 V. The RFVGA demonstrates high linearity (THD ≈ -60 dB) and noise immunity (average Noise Figure ≤ 6 dB). It has an input referred third-order intercept point (IIP3) of -1.5 dBm, and an input reflection coefficient (S11) under -8 dB within the frequency band of interest. Also, it dissipates around 5 mW using a 1.2 V power supply. Further, Monte Carlo simulations incorporating process, supply voltage and temperature variations (PVT variations) as well as mismatch between devices (based on width and length of devices) indicate that the design is quite robust. The proposed RFVGA is highly suitable for mobile digital television (DTV) tuner applications.

This paper explores the use of notch filters for the purpose of damping out chaotic oscillations. The design of the filter and the way it is interfaced to the system are investigated from a signal-processing point of view. A Chua's circuit, that has typical applications in synchronization and secure communications, is used to exemplify the suggested methodology where both theoretical and experimental results are provided. The power spectrum of the original system is analyzed to selectively damp-out portions of the power spectrum, thus truncating period-doubling, the original cause of chaos. Both single and double notch filters are explored to examine their effect on the performance of the modified system. Steady state analysis as well as issues regarding practical implementation are addressed and advantages and limitations of the proposed method are highlighted.

Planar PCB inductors, being printed directly on the PCB board, are employed in various electronic systems. The resistance and inductance of a square PCB inductor are calculated in this paper. For this a multiconductor transmission-line model is constructed and its coupling integral equations are given. These equations are solved by wavelet-MoM, in which a [0, 1] Coifman intervallic scarlet is used. Finally, the inductance and resistance versus frequency plots are presented.