Narrow Results

Optimization of power consumption is one of the main design challenges in today's low-power high-speed analog integrated circuits. In this paper, two popular techniques to stabilize two-stage operational amplifiers, namely, Miller and cascode compensations are compared from power efficiency point of view. To accomplish this, cascode-compensated topologies are basically analyzed to derive the required equations for the comparison. In the analysis, a new method to take into account the effect of transfer function zeros is proposed. By assuming that the zeros' magnitudes are fairly nondominant, the method increases the accuracy of the analyses. The relationships show that for the same specifications, cascode compensation is more power-efficient than Miller compensation, especially for heavy capacitive loads. This has been confirmed by SPICE simulations.

This work proposes and develops an original compensation approach for low-power three-stage operational transconductance amplifiers driving large capacitive loads. The proposed solution is based on the basic reversed nested Miller compensation and exploits a voltage buffer and two nulling resistors in the compensation network, along with a feedforward stage to improve slewing and settling performance. A well-defined design procedure using the loop gain phase margin as the main design parameter is also developed. SPECTRE simulations on a three-stage amplifier are carried out and are found to be in excellent agreement with the theoretical analysis, showing a significant improvement of the proposed approach over traditional compensation strategies in terms of small-signal and large-signal performance. Monte Carlo simulation results finally prove the proposed technique to be well-guarded against process parameter variations.

This paper presents two novel active-feedback single Miller capacitor frequency compensation techniques for low-power three-stage amplifiers. These techniques include the active-feedback single Miller capacitor frequency compensation (AFSMC) and the dual active-feedback single Miller capacitor frequency compensation (DAFSMC). In the proposed techniques, only one Miller capacitor in series with a current buffer is utilized. The main advantages of the proposed three-stage amplifiers are the enhanced unity-gain bandwidth and the reduced silicon area. Small-signal analyses are performed and the design equations are obtained. Extensive HSPICE simulation results are provided to show the usefulness of the proposed AFSMC and DAFSMC amplifiers in both large and small capacitive loads.

A low dropout (LDO) linear regulator with pre-regulator is presented in this paper. The LDO is suitable for wide power supply of 4.5–28 V for smart battery system applications to generate a stable 1.8 V output. The proposed LDO provides high stability by pre-regulator for a rough 3.3 V as internal power supply and multi-zero and multi-pole frequency compensation. The scheme of combining of using output capacitor to set a dominant pole, utilizing a buffer stage to avoid generation of low-frequency pole, introducing an additional zero, is presented to stabilize the regulator loop for various load conditions and wide supply range. Besides, parasitic poles in high frequency can be compensated by feed-forward compensation and mirror-pole compensation.

Nano-scale area-efficient MOS devices are employed in this article to stabilize high-speed operational amplifiers (opamps) for those applications that deal with negative feedback. As an alternative choice, metal-insulator-metal (MIM) capacitors cannot be integrated in every technology as they require additional process masks. Moreover, these components suffer from large silicon area. In this paper, considerations of a successful MOSFET-only amplifier design are highlighted and described. These considerations make it possible to fabricate these amplifiers for a nano-scale digital system-on-chip (SoC). Circuit-level simulations include comparison between MOS capacitors (MOSCAPs) with MIM capacitors (MIMCAPs) in two identical processes. The efficiency of the given design considerations are also validated through simulation in 90-nm CMOS technology. A MOSFET-only amplifier is designed as the main part of a 5 MS/s sample-and-hold. Using the proposed design techniques, the MOSFET-only amplifier with Miller compensation recovers 51% silicon die with respect to a MIMCAP amplifier for identical signal-to-noise-plus-distortion (SNDR) ratio.

Bandwidth limitation is a vital problem for high-speed data transmission in logging cable telemetry systems (LCTSs). This paper proposes a frequency compensation method with an analog circuit design, possessing high flexibility and robustness. Analytical expressions are derived for the relationship between pole-zero and gain, deviations caused by high temperature; and are then verified via simulation. To address the efficacy of the circuit design, a real case with low computation complexity and high accuracy is proposed and employed. The case of a 7km LCTS shows frequency compensation with a 200% bandwidth expansion — from 160kHz at $-$55dB of the original cable to 300kHz at $-$3dB — and a 60dB improvement in high frequency gain. After comparing the signals with and without compensation, the improvements in transmission performance by the proposed pre-emphasis circuit and equalizer are confirmed.

A four-stage operational transconductance amplifier (OTA) with a novel compensation structure combining multipath $G_m$-$C$ compensation and no capacitor feed-forward compensation is proposed in this paper. Based on the small-signal model, stability analysis and design consideration are carried out to demonstrate the stability of the compensation technique. To verify the effectiveness of the compensation scheme, the proposed OTA which drives a 2 pF capacitance, is simulated in TSMC 65nm 1.2V CMOS process, achieving 808MHz gain-bandwidth, 119dB DC gain, 585V/$\mu$s slew rate (SR) and 6 ns 1% settling time. The circuit is operated at the single supply voltage of 1.2V with power consumption of 2.17mW and the layout area is 0.011mm².

The importance of a transimpedance amplifier in an optical transceiver is very well known. In this paper, a novel CMOS design of the bulk-driven transimpedance amplifier (BD-TIA) is given where the bridge-shunt peaking-based frequency compensation technique is exploited to improve frequency response. A pre-existing active inductor has been used for the same. The electrical characteristics and functioning of this inductor simulator make it a suitable alternative to both floating and grounded spiral inductors. In order to verify the workability of the proposed circuit, it has been simulated with TSMC CMOS 0.18$\mu$m process parameters. The proposed circuit is useful in low-voltage low-power VLSI applications as it uses a single supply of 0.75V. The power consumption of BD-TIA is very low, being 0.37mW, because a standard MOSFET has been replaced by a bulk-driven MOSFET (BDMOS), while the 3-dB bandwidth is observed to be 4.5GHz. The mathematical investigation and small signal analysis show that the simulation results are in good agreement.

This work presents an effective and straightforward frequency compensation scheme in CMOS three-stage amplifiers. Using a differential block in the compensation network, the proposed circuit shows independent and large first dominant pole regarding the DC gain path. The presented three-stage architecture is frequency-compensated just by a single Miller capacitor. Mathematical analysis is presented along with ample simulations that are performed using TSMC 0.18-$\mu$m CMOS technology. According to the results, the proposed circuit shows DC gain equal to 118dB, GBW equal to 466MHz, PM equal to 74.3^∘ and 1.2mW as power consumption, respectively. The high values of DC gain and GBW make the proposed amplifier appropriate for more speedy operations such as high-speed modulators and data converters.

In this paper, an efficient frequency compensation method is investigated for a four-stage CMOS amplifier. The frequency compensation network includes two sets of capacitors at the differential block output. The proposed compensated amplifier is described symbolically to obtain the transfer function. Meanwhile, the proposed configuration is designed at the circuit level and is simulated via 0.18$\mu$m CMOS technology. Compared to the other existing methods, the proposed amplifier satisfies the figure of merits considerably. This stems from the fact that lower capacitor values are used to perform compensation, leading to lower die occupation, and reach boosted gain bandwidth products. Leveraging both the configuration and design procedure, a high-performance four-stage is presented in this paper.

The rapid advancements of CMOS integrated circuits technologies lead designers to cascade structures and avoiding cascode amplifiers. As a result, frequency compensation becomes the most important issue since multi-stage amplifiers are highly potential to instability. Here in this work, two differential stages are exploited to form frequency compensation network. These stages realize four Miller loops and share each Miller capacitor in two loops simultaneously. This intensifies Miller effect to improve frequency response due to pole-zero cancellation. The proposed three stage amplifier is modeled symbolically via a transfer function (TF) while 0.18um CMOS technology is used for circuit simulation. Good agreement between theoretical calculation and simulation results shows validity and accuracy of the TF. Also ample simulations are performed to exhibit the proposed amplifier performance against parameters mismatches. The proposed three stage amplifier expresses 105 dB as DC-gain, 4.8 MHz as Gain Band Width and 72 degree as Phase Margin. The amplifier consumes 360 uW as power consumption. This performance obviously is an improvement of Nested Miller Compensation (NMC) while Figure of Merits (FoMs) are enhunced.