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Particle Swarm Optimization Design of Low-Power Multistage Amplifier using g_m/I_D Methodology

School of Electronic and Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin, 300072, China

E-mail Address: zhanggy@tju.edu.cn

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Xia Xiao

School of Electronic and Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin, 300072, China

E-mail Address: xiaxiao@tju.edu.cn

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Jiangtao Xu

School of Electronic and Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin, 300072, China

E-mail Address: xujiangtao@tju.edu.cn

Corresponding author.

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Kaiming Nie

School of Electronic and Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin, 300072, China

E-mail Address: nkaiming@tju.edu.cn

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, and

Zhiyuan Gao

School of Electronic and Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin, 300072, China

E-mail Address: gaozhiyuan@tju.edu.cn

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https://doi.org/10.1142/S0218126616501048Cited by:2 (Source: Crossref)

Abstract

A design flow using the $g_{m}$ $g_{m}$ / $I_{D}$ $I_{D}$ methodology with the adaptive particle swarm optimization (PSO) algorithm is proposed for the modern analog circuit in this paper. For the advanced CMOS process, $g_{m}$ $g_{m}$ / $I_{D}$ $I_{D}$ methodology is suitable to the long channel and short channel design in all transistor operation regions. Different from the classical PSO algorithm, the adaptive PSO algorithm features the better search efficiency and faster convergence speed over the global search. Two amplifiers were designed and implemented in a standard 0.11 $μ$ $μ$ m CMOS process using MATLAB and HSPICE. Using the thermal noise coefficient $γ$ $γ$ and the corner frequency $f_{corner}$ $f_{corner}$ , this paper explored the noise design budget of low-power multistage amplifier in different saturation modes. Detailed optimization of the objective function and constraints are classified into the mono-objective case and the multi-objective case. The total running times of simulations are 5649 s and 6813 s while the errors are less than 9% and 10%, respectively. Compared with CODE, GA $+$ $+$ PF and DE $+$ $+$ PF algorithms, it can save more running time and improve the accuracy of the design. Moreover, it provides more design freedom for the trade-off among gain, the gain-bandwidth (GBW) product, noise and the phase margin under worst cases without extra tweaking. Not only can the methodology work in the 0.18 $μ$ $μ$ m CMOS process, but also be migrated to the 0.11 $μ$ $μ$ m CMOS process, even in the nanometer analog circuit.

This paper was recommended by Regional Editor Piero Malcovati.

Keywords:

References

1. K. Laker and W. Sansen, Design of Analog Integrated Circuits and Systems, 1st edn. (McGraw-Hill, New York, 1994). Google Scholar
2. F. D. Bernardinis, P. Nuzzo and A. S. Vincentelli, Mixed signal design space exploration through analog platforms, Proc. 42nd Ann. Design Automation Conf. (2005), pp. 875–880. Google Scholar
3. F. Leyn et al., Analog circuit sizing with constraint programming modeling and minima optimization, Proc. IEEE ISCAS (1997), pp. 1500–1503. Google Scholar
4. T. Massier, H. Graeb and U. Schlichtmann, The sizing rules Method for CMOS and bipolar analog integrated circuit synthesis, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 27 (2008) 2209–2222. Crossref, Web of Science, Google Scholar
5. F. Perez-Montes et al., A SPICE based, portable, user-friendly cell-level sizing tool, Proc. IEEE Design, Automation and Test in Europe Conf. and Exhibition (DATE) (2000), p. 739. Google Scholar
6. G. Gielen et al., ISAAC: A symbolic simulator for analog integrated circuits, IEEE J. Solid-State Circuits 24 (1989) 1587–1597. Crossref, Web of Science, Google Scholar
7. G. Gielen and R. A. Rutenbar, Computer–aided design of analog and mixed–signal integrated circuits, Proc. IEEE 88 (2000) 1825–1854. Crossref, Web of Science, Google Scholar
8. F. Silveira et al., A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a Silicon-on-Insulator micropower OTA, IEEE J. Solid–State Circuits 31 (1996) 1314–1319. Crossref, Web of Science, Google Scholar
9. D. Flandre et al., Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology, IEEE J. Solid–State Circuits 32 (1997) 1006–1012. Crossref, Web of Science, Google Scholar
10. D. Foty et al., Starting over: gm/ID-based MOSFET modeling as a basis for modernized analog design methodologies, Technical Proc. 2002 Int. Conf. Modeling and Simulation of Microsystems (2002), pp. 682–685. Google Scholar
11. A. Ayed et al., Design and optimization of CMOS OTA with gm/ID methodology using EKV model for RF frequency synthesizer application, Proc. IEEE 12th Int. Conf. Electronics, Circuits and Systems (ICECS) (2005), pp. 1–5. Google Scholar
12. A. Girardi et al., A tool for automatic design of analog circuits based gm/ID methodology, Proc. IEEE ISCAS (2006), pp. 4–8. Google Scholar
13. A. Girardi et al., Power constrained design optimization of analog circuits based on physical gm/ID characteristics, Proc. IEEE 19th Ann. Symp. Integrated Circuits and Systems Design (SBCCI) (2006), pp. 89–93. Google Scholar
14. D. M. Binkley et al., Tradeoffs and optimization in analog CMOS design, Proc. IEEE 14th Int. Conf. Mixed Design of Integrated Circuits and Systems (MIXDES) (2007), pp. 47–60. Google Scholar
15. H. D. Dammak et al., Design of folded cascode OTA in different regions of operation through gm/ID methodology, World Acad. Sci. Eng. Technol. 45 (2008) 28–33. Google Scholar
16. P. Jespers, A gm/ID Methodology: A Sizing Tool for Low-Voltage Analog CMOS Circuits (Springer, New York, 2009). Google Scholar
17. K. Takayuki et al., Design optimization of high-speed and low-power operational trans-conductance amplifier using gm/ID look–up table methodology, IEICE Trans. Electron. E94–C (2011) 334–345. Crossref, Web of Science, Google Scholar
18. J. Dréo, A. Petrowski and P. Siarry, Metaheuristics for Hard Optimization: Methods and Case Studies (Springer, New York, 2006). Google Scholar
19. J. B. Grimbleby et al., Automatic analogue circuit synthesis using genetic algorithms, IEE Proc.-Circ. Dev. Syst. 6 (2000) 319–323. Crossref, Google Scholar
20. J. P. Courat et al., Electronic component model minimization based on log simulated annealing, IEEE Trans. Circuits Syst. I, Reg. Papers 41 (1994) 790–795. Google Scholar
21. J. Kennedy et al., Particle swarm optimization, Proc. IEEE Int. Conf. Neural Networks (ICNN) (1995), pp. 194–1948. Google Scholar
22. M. Clerc, Particle Swarm Optimization (John Wiley & Sons, New York, 2010). Google Scholar
23. F. Mourad, Y. Cooren and A. Sallem et al., Analog circuit design optimization through the particle swarm optimization technique, Analog Integr. Circuits. Signal. Process. 63 (2010) 71–82. Crossref, Web of Science, Google Scholar
24. X. Hu et al., Adaptive particle swarm optimization: Detection and response to dynamic systems, Proc. IEEE World on Congr. Computational Intelligence (WCCI) (2002), pp. 1666–1670. Google Scholar
25. K. Yasuda et al., Adaptive particle swarm optimization, IEEE Int. Conf. Systems, Man and Cybernetics (SMC) (2003), pp. 1554–1559. Google Scholar
26. B. K. Panigrahia, V. R. Pandi and S. Das, Adaptive particle swarm optimization approach for static and dynamic economic load dispatch, Energy. Convers. Manage. 49 (2008) 1407–1415. Crossref, Web of Science, Google Scholar
27. Z. Zhan et al., Adaptive particle swarm optimization, IEEE Trans. Syst. Man Cybern. B, Cybern. 39 (2009) 1362–1381. Crossref, Web of Science, Google Scholar
28. C. Li and S. Yang, An adaptive learning particle swarm optimizer for function optimization, Proc. IEEE Congr. Evolutionary Computation (CEC) (2009), pp. 381–388. Google Scholar
29. X. Li, Adaptively choosing neighborhood bests using species in a particle swarm optimizer for multimodal function optimization, Proc. IEEE Genetic and Evolutionary Computation–Conf. (GECCO) (2004), pp. 105–116. Google Scholar
30. M. Hu et al., An adaptive particle swarm optimization with multiple adaptive methods, IEEE Trans. Evol. Comput. 17 (2013) 7050–720. Crossref, Web of Science, Google Scholar
31. M. Hu et al., An intelligent augmentation of particle swarm optimization with multiple adaptive methods, Inform. Sci. 213 (2012) 68–83. Crossref, Web of Science, Google Scholar
32. T. Beck et al., Numerical thermal mathematical model correlation to thermal balance test using adaptive particle swarm optimization (APSO), Appl. Therm. Eng. 38 (2012) 168–174. Crossref, Web of Science, Google Scholar
33. K. H. Youssef et al., Adaptive fuzzy APSO based inverse tracking–controller with an application to DC motors, Expert Syst. Appl. 36 (2009) 3454–3458. Crossref, Web of Science, Google Scholar
34. P. Q. Guillaume et al., A modified gm/ID design methodology for deeply scaled CMOS technologies, Analog. Integr. Circuits Signal Process. 78 (2014) 771–784. Crossref, Web of Science, Google Scholar
35. B. Murmann et al., Design and optimization of operational transconductance amplifiers in fine–line CMOS, IEEE Custom Integrated Circuits Conf.(CICC) (2008) Educational Session. Google Scholar
36. B. Murmann et al., Operational transconductance amplifier design, Stanford University EE315A Course Reader (2010), pp.188–281. Google Scholar
37. J. Ou and P. M. Ferreira, A gm/ID based noise optimization for CMOS folded cascode operational amplifier, IEEE Trans. Circuits Syst. II, Exp. Briefs 61 (2014) 783–787. Crossref, Web of Science, Google Scholar
38. P. G. A. Jespers and B. Murmann, Calculation of MOSFET distortion using the transconductance to current ratio (gm/ID), IEEE ISCAS (2015), pp. 529–532. Google Scholar
39. F. T. S. Chan et al., Swarm Intelligence: Focus On Ant and Particle Swarm Optimization (I–Tech Education and Publishing, Vienna, 2007). Google Scholar
40. C. R. Raquel et al., An effective use of crowding distance in multiobjective particle swarm optimization, Proc. IEEE Genetic and Evolutionary Computation–Conf. (GECCO) (2005), pp. 257–264. Google Scholar
41. C. A. Coello-Coello et al., MOPSO: A proposal for multiple objective particle swarm optimiza-tion, IEEE CEC (2002), pp. 1051–1056. Google Scholar
42. B. Liu et al., Analog circuit optimization system based on hybrid evolutionary algorithms, Integration 42 (2009) 137–148. Crossref, Web of Science, Google Scholar
43. J. Ou and P. M. Ferreira, A unified explanation of gm/ID based noise analysis, J. Circuit. Syst. Comp. 24 (2015) 1550010-1–1550010-13. Link, Web of Science, Google Scholar
44. G. Zhang et al., Low-power three-stage amplifier using active–feedback miller capacitor and serial RC frequency compensation, Trans. Tianjin Univ. 21 (2015) 515–523. Crossref, Google Scholar
45. M. Tan et al., A cascode miller-compensated three-stage amplifier with local impedance attenuation for optimized complex-pole control, IEEE J. Solid-State Circuits 50 (2015) 440–449. Crossref, Web of Science, Google Scholar
46. A. Shameli et al., A novel power optimization technique for ultra–low power RFICs, Pro. ISLPED (2006), pp. 274–279. Google Scholar
47. M. Parvizi et al., A Sub-mW Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23 (2015) 1111–1122. Crossref, Web of Science, Google Scholar
48. W. Sansen, Analog Design Essentials (Springer, New York, 2007). Google Scholar

Vol. 25, No. 09

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History

Received 1 September 2015

Accepted 9 March 2016

Published: 3 May 2016

Keywords

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Particle Swarm Optimization Design of Low-Power Multistage Amplifier using g_m/I_D Methodology

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Particle Swarm Optimization Design of Low-Power Multistage Amplifier using gm/ID Methodology

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