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New Design of Scan Flip-Flop to Increase Speed and Reduce Power Consumption

Ramin Razmdideh

Department of Electrical Engineering, Shahid Bahonar University of Kerman, Kerman, Iran

Corresponding author.

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Ali Mahani

Department of Electrical Engineering, Shahid Bahonar University of Kerman, Kerman, Iran

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, and

Mohsen Saneei

Department of Electrical Engineering, Shahid Bahonar University of Kerman, Kerman, Iran

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https://doi.org/10.1142/S0218126615501595Cited by:2 (Source: Crossref)

Abstract

In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented, in which short circuit current is controlled. Switching activity is decreased to reduce the consumed power of the scan flip-flop. Also, the total number of transistors through the path from input to the output is reduced and so the delay of the proposed scan flip-flop is decreased. Simulation results show 12% and 29% reduction in power consumption and delay of the proposed scan flip-flop, respectively. The results are given by comparison of our work with other scan flip-flops at 50% data switching activity.

This paper was recommended by Regional Editor Piero Malcovati.

Keywords:

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