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Increasing the operating speed of the trains on modern networks necessitates performing dynamic analyses to assess the performance of bridges under passage of trains. The detailed investigation of their responses requires constructing complex computational models capable to take the train–track–bridge interaction effects into account. Such models have successfully been developed; however, employing those elaborated models for practical engineering applications, or to perform studies that require a large number of analyses may become infeasible. Among such situations are conducting probabilistic investigations, screening of entire networks, or sensitivity analyses. These concerns have been addressed by employing simplified models mostly relying on moving load modeling strategy which disregards the train–track–bridge interaction effects. Those neglected contributions can be compensated by implementing additional correction factors. The distribution of loads within track is one of those disregarded effects where a reduction factor is recommended by design guidelines to take its contribution into account. It has been shown that the existing relationship for these reduction factors delivers an acceptable performance for vertical accelerations, while showing a less favorable performance for displacements. Then, a data-driven strategy is adopted in this study to propose easy-to-apply relationships for reduction factors of deflections, due to load distribution within the track. In this context, three different distributive lengths of triangular load footprints have been considered, namely 2.0, 2.5 and 3.0m. The procedure employed has trained and tested for more than 1200 train configurations, comprising conventional, articulated and regular vehicles, and including several tens of thousand data points for each distributive length. The performance observed in the new models revealed a considerable improvement with respect to the existing relationship.

In this paper, a logic style that is becoming increasingly popular is presented, which is called MOS Current Mode Logic (MCML). MCML is a novel and useful logic style for high-speed, low-power and mixed-signal applications. Its high-speed switching, low supply voltage and reduced output voltage swing contribute to its high performance, low power dissipation, and low noise features. MCML circuits are compared to several other logic styles, such as conventional static CMOS, dynamic logic, and traditional emitter coupled logic (ECL) in terms of power, delay and common mode noise immunity. MCML circuits seem to be very promising in high-speed, low-power and mixed-signal digital circuit applications, such as portable electronic devices, gigahertz microprocessors, and optical transceivers.

A miniature disk-pivot piezoelectric motor using a vibration mode B₁₁ of one nodal circle and one nodal diameter was investigated. Different from conventional wobble-type piezoelectric motor using piezoelectric rod or cylinder, a metal/piezoelectric disk is used to simulate the wobble vibration and an embedded metal cylinder is used to amplify the transverse displacement to obtain a much higher revolution speed over 10,000 rpm through the contact friction between the stator and rotor. The outer diameter of the metal/piezoelectric disk and the embedded cylinder is 14 mm and 2.5 mm, respectively. In order to avoid the coupling between the B₁₁ and any other vibration modes, the structure of the stator is analyzed using Finite Element Method (FEM) and optimized to avoid the influence between them. The simulations show that the stability of the disk-pivot piezoelectric motor will be influenced greatly when any other vibration mode is close to the mode B11. To separate the coupling modes, two structure parameters can be modified: the thickness of the piezoelectric ceramic and the height of the middle metal cylinder on the stator. And these methods were proved through testing some prototypes of the motors.

A new method is proposed to improve the response time of organic photodetectors by using displacement current. By inserting a transparent organic dielectric layer between the organic semiconductor active layer and the electrode the displacement current will be produced and replace the conduction current for current propagation, which will overcome the disadvantage of low carrier mobility of organic semiconductors. Under the irradiation of nanosecond pulse laser the rise time and fall time of the organic photodetector based on displacement current decrease 10% and 86%, respectively comparing to the conventional organic photodetector based on conduction current, which indicates the displacement current could renew the operation principle for high-speed organic photodetectors.

In this paper, a new Simultaneous Bi-directional Data Bus architecture has been presented. The new architecture provides stable and consistent impedance matching to the transmission channel, which can significantly reduce reflections and ensure the signal integrity and transmission reliability. To validate the design, an in-depth comparative study has been performed.

The present paper addresses an improved low-power high-speed buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output voltage of the input differential amplifier and outputs an additional current signal providing slew-rate enhancement at the output stage. Post-layout simulations show that the proposed buffer can drive a 1 nF column line load with 8.5 V/μs slew-rate and 0.8 μs settling time, while drawing only 8 μA static current from a 3 V power supply.

A new 1-bit hybrid Full Adder cell is presented in this paper with the aim of reaching a robust and high-performance adder structure. While most of recent Full Adders are proposed with the purpose of using fewer transistors, they suffer from some disadvantages such as output or internal non-full-swing nodes and poor driving capability. Considering these drawbacks, they might not be a good choice to operate in a practical environment. Lowering the number of transistors can inherently lead to smaller occupied area, higher speed and lower power consumption. However, other parameters, such as robustness to PVT variations and rail-to-rail operation, should also be considered. While the robustness is taken into account, HSPICE simulation demonstrates a great improvement in terms of speed and power-delay product (PDP).

A high speed low power latched comparator is presented. The bipolar junction structures are used to enhance latch speed, and the controller is proposed to reduce latch current drain while providing complementary metal oxide semiconductor (CMOS) level latch signals. The measured delay time of the comparator is 132.5 ps and the power consumption is 127 μW at 100 MHz. The proposed circuit is used in a 14-bit 100-MSPS SHA-Less pipelined ADC, and is designed by ASMC 0.35-μm 3.3 V BiCMOS technology.

A high-speed and high-accuracy continuous-time common-mode feedback block (CMFB) is presented. To satisfy speed and accuracy requirements, some modifications have been applied on differential difference amplifier (DDA) CMFB circuit. The proposed method is applied to a folded cascode op-amp with power supply of 3.3 V. In order to verify the proposed circuit, simulations are done in 0.35 μm standard CMOS technology. In the worst condition when the output common-mode (CM) voltage is initialized to VCC or GND, only 1.1 ns is required to set the output CM voltage on the desired level. Also in a wide range of input CM voltage variations, the deviation of the output CM voltage from reference voltage is less than 6 mV, so simulation results confirm the expected accuracy and speed while simultaneously the proposed CMFB circuit preserves other characteristics of DDA CMFB circuit such as unity gain frequency, 3-dB bandwidth, phase margin and linearity.

In this paper, a novel accurate analog-based 50% duty cycle corrector (DCC) for high-speed and high-resolution operations is presented. Due to the performance limitations of conventional DCCs, such as a confined locking range and overtone locking, a novel delay line using forward-body-bias technique and reset circuit are adopted to enlarge the locking range of the proposed DCC. Simulated results based on the standard 0.18 μm 1.8 V standard CMOS process show that output duty cycle error is less than ±1% over an input frequency range of 50–800 MHz. The peak-to-peak jitter at 800 MHz is 789.77 fs with a power consumption of 11.09 mW. The active layout area of the proposed DCC is 0.21 × 0.21 mm².

In this paper, a novel low-power and high-speed pulse triggered scan flip-flop is presented, in which short circuit current is controlled. Switching activity is decreased to reduce the consumed power of the scan flip-flop. Also, the total number of transistors through the path from input to the output is reduced and so the delay of the proposed scan flip-flop is decreased. Simulation results show 12% and 29% reduction in power consumption and delay of the proposed scan flip-flop, respectively. The results are given by comparison of our work with other scan flip-flops at 50% data switching activity.

Frequency dividers are used in frequency synthesizers to generate specific frequencies or clock (CK) waveforms. As consequences of their operating principles, frequency dividers often produce output waveforms that exhibit duty cycles other than 50%. However, some circuits and systems, including dynamic memory systems and data converters, which accommodate frequency divider outputs, may need symmetric or 50%-duty-cycle clock waveforms to optimize timing margins or to obtain sufficient timing reliability. In this review paper, design principles and methods are studied to produce symmetric waveforms for the in-phase (I) and quadrature (Q) outputs of high-speed CMOS frequency dividers with design considerations from the logic gate level down to the transistor level in terms of speed, reliability, noise, and latency. A compact and robust multi-gigahertz frequency divider with moduli 12, 14, and 16 to provide I and Q outputs with 50% duty cycle is proposed and designed using a 90-nm digital CMOS process technology with 1.2-V supply.

This paper presents a statistically-driven two-step flash sub-analog-to-digital converter (ADC) to construct the high-speed time-interleaved ADC in wireline communication applications. The comparators in the flash sub-ADC are divided into the large probability first stage and the small probability second stage to take advantage of the nonuniform probability distribution of the input signal. At the first step of operation, the large probability first stage is activated while the small probability second stage is suspended. If the input signal is beyond the input range of the first stage, the segment selection signal will trigger proper segment in the second stage. Feed-forward equalization is proposed to manipulate the probability distribution of the ADC input signal. A possible implementation of the proposed ADC as well as the modulation and equalization scheme is presented to comply with the IEEE 802.3ap 10G Ethernet standard. In the case of a PAM-4 pseudorandom signal, the proposed solution achieves $66\%$ reduction on the average number of activated comparators compared to a conventional flash ADC.

The need of energy-efficient, high-speed, and low-offset analog-to-digital converters is forcing to design the dynamic latch comparators to enhance the speed and energy efficiency with minimum offset. This paper presents a novel double tail dynamic latch comparator using bulk-driven process and common-gate (CG) amplifier in amplification stage. The gain of amplification stage is enhanced using GACOBA load in which gain is controlled by bulk amplification through CG amplifier. It results in remarkable enhancement in regeneration speed and reduction in power consumption. The analytical expressions of delay and offset due to mismatch are also derived. These derivations explore the key contributors to reduce the delay and offset of proposed comparator. The outcomes are verified in CADENCE SPECTRE at 45-nm CMOS process technology through various simulations and Monte-Carlo analysis at different process corners. The post-layout analysis validates the simulation results. The proposed comparator is 93% more energy-efficient and lessens more than 84% delay in comparison of conventional design. The 1–$\sigma$ input offset voltage and average input voltage error due to kickback noise are 2.48mV and 0.824$\mu$V, respectively at 0.8V power supply with 34.32$\mu$m² active area.

An ultra-wide bandwidth fully differential two-stage 65nm CMOS operational amplifier (Opamp) is presented, which uses a novel bandwidth extension technique called “pole duplication”. This technique is based on relocating the dominant pole with the same location with a non-dominant pole and adjusting 3-dB frequency and stability with a compensation network. Simulation results show that the proposed Opamp has 103MHz 3-dB bandwidth with a 2pF load capacitor. It consumes 9mA current from 1.2-V supply. Transition frequency of 2.4GHz and a gain of 29dB is accomplished. A 2pF load capacitance can be driven at a phase margin of $55^{\circ }$. The suggested pole duplication technique is used to achieve higher 3-dB cut-off frequencies by adjusting the load capacitor. Fully differential two-stage Opamp is presented, which uses a novel bandwidth extension technique, is suitable for SoC active filter applications with 40$\mu \mathrm{\text{m}}\times 60\mu$m layout area and ultra-wide 3-dB bandwidth.

This paper presents a novel footless single clock-phase three-stage comparator with internally generated regenerative voltage signals for low kickback noise and high speed. The preamplifier and clocked latch topology of dynamic comparators are considered in this brief. The proposed design has been compared by analyzing and optimizing three state-of-the-art comparator designs: Modified StrongARM, Miyahara’s and Three-Stage. These designs are simulated using the 40nm CMOS technology process. The area of the proposed comparator is 28.025$\mu$m². When simulated in the SPICE-based simulator HSPICE, under typical performance conditions of 0.9V supply voltage, 25^∘C, 1 GHz operational frequency, typical process corner (tt), and 1mV differential voltage, the proposed comparator produces the best post-layout results, with a minimum delay of 59.9ps from meta-stability analysis, energy per comparison of 0.175pJ/comparison and a kickback noise of 44.55 $\mu$A. The proposed design also shows a significant improvement in the measured performance parameters over the other state-of-the-art dynamic comparators that have been discussed in this brief. The obtained results show that the proposed comparator is appropriate for 12-bit Successive Approximation Resister Analog-to-Digital Converters (SAR-ADCs) in IoT applications.

In this paper, a logic style that is becoming increasingly popular is presented, which is called MOS Current Mode Logic (MCML). MCML is a novel and useful logic style for high-speed, low-power and mixed-signal applications. Its high-speed switching, low supply voltage and reduced output voltage swing contribute to its high performance, low power dissipation, and low noise features. MCML circuits are compared to several other logic styles, such as conventional static CMOS, dynamic logic, and traditional emitter coupled logic (ECL) in terms of power, delay and common mode noise immunity. MCML circuits seem to be very promising in high-speed, low-power and mixed-signal digital circuit applications, such as portable electronic devices, gigahertz microprocessors, and optical transceivers.

We discuss the gravitational collapse of cylindrically distributed two dust fluid system using high-speed approximation scheme. This provides the generalization of the results already given by Nakao and Morisawa for the dust fluid.