No Access

LOW-POWER EIGHT-BIT SCSDL CLA WITH A NOVEL SPLIT-LEVEL CHARGE-SHARING DIFFERENTIAL LOGIC (SCSDL)

ROBERT C. CHANG

Department of Electrical Engineering, National Chung Hsing University, Taichung City 402, Taiwan, ROC

No. 250, KuoKuang Road, South District, Taichung City 402, Taiwan, ROC.

Search for more papers by this author

HSIN-LEI LIN

Department of Electrical Engineering, National Chung Hsing University, Taichung City 402, Taiwan, ROC

Search for more papers by this author

, and

I-HAO WANG

Lite-On Technology Corporation, Hsin Chu City 300, Taiwan, ROC

4F, No. 338, Peita Road, Hsin Chu City 300, Taiwan, ROC.

Search for more papers by this author

https://doi.org/10.1142/S0218126607003733Cited by:0 (Source: Crossref)

Abstract

A novel logic family, called Split-Level Charge-Sharing Differential Logic (SCSDL), is proposed in this letter. The SCSDL uses the charge recycling technique to reduce power dissipation of differential logic in the precharge phase. The simulation results show that the SCSDL has the best power-delay product compared to several other differential logic families. An eight-bit carry lookahead adder (CLA) designed using the proposed SCSDL can reduce at least 30.64% of power-delay product compared to DCVSL CLA dissipation. A test chip was fabricated to illustrate the feasibility of the SCSDL circuit.

Keywords:

References

L. G. Helleret al., Cascode voltage switch logic: A differential CMOS logic family, Proc. IEEE Int. Solid-State Circuits Conf. (1984) pp. 16–17. Google Scholar
S.-L. Lu, IEEE J. Solid-State Circuits 23, 1013 (1988), DOI: 10.1109/4.354. Crossref, Web of Science, Google Scholar
D. Somasekhar and K. Roy, IEEE J. Solid-State Circuits 31, 981 (1996), DOI: 10.1109/4.508212. Crossref, Web of Science, Google Scholar
K. M. Chu and D. L. Pulfrey, IEEE J. Solid-State Circuits 22, 528 (1987), DOI: 10.1109/JSSC.1987.1052767. Crossref, Web of Science, Google Scholar
K. Bernsteinet al., High Speed CMOS Design Style (Kluwer Academic Publishers, 1999) pp. 111–112. Crossref, Google Scholar
B.-S. Konget al., IEEE J. Solid-State Circuits 21, 1267 (1996). Google Scholar
J. Park, J. Lee and W. Kim, IEEE J. Solid-State Circuits 34, 904 (1999), DOI: 10.1109/4.766829. Crossref, Web of Science, Google Scholar
Y. Moisiadis, I. Bouras and A. Avapoyanni, A CMOS differential logic for low-power and high-speed applications, IEEE Int. Symp. Circuits and Systems4 (2001) pp. 140–143. Google Scholar
D. Somasekhar and K. Roy, IEEE Trans. VLSI Syst. 6, 573 (1998), DOI: 10.1109/92.736130. Crossref, Google Scholar
J. Park, J. Lee and W. Kim, Current sensing differential logic (CSDL) for low-power and high-speed systems, IEEE Int. Symp. Circuits and Systems2 (1998) pp. 129–132. Google Scholar
A. Bellaouar and M. Elmasry , Low-Power Digital VLSI Design: Circuits and Systems ( Kluwer , Norwell , 1995 ) . Crossref, Google Scholar