Journal of Circuits, Systems and Computers

This paper addresses the pilot-aided multiuser least square (LS) channel estimation for the uplink of multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) systems. The systems under consideration allow all users use all available subcarriers independently and thus involve multiuser interference in the frequency domain. Direct application of the known pilot-aided single-user channel estimation methods to these systems is prohibited, requiring much more new investigations. The decentralized and centralized channel estimation algorithms are developed according to different multiuser scenarios. Optimal multiuser pilots are proposed, especially for centralized estimation methods with respect to the mean square error (MSE) of LS channel estimate. In addition, channel tracking algorithms are represented in terms of individual user's channels.

In this paper, a measure of sensitivity is defined to evaluate fault tolerance of neural networks and we show that the sensitivity of a link is closely related to the amount of information passed through it. Based on this assumption, we prove that the distribution of output error caused by s-a-0 (stuck at 0) faults in an MLP network has a Gaussian distribution function. UDBP (Uniformly Distributed Back Propagation) algorithm is then introduced to minimize mean and variance of the output error. Then an MLP neural network trained with UDBP, contributes in an Algorithm-Based Fault Tolerant (ABFT) scheme to protect a nonlinear data process block. A systematic real convolution code guarantees that faults representing errors in the processed data will result in notable nonzero values in syndrome sequence. A majority logic decoder can now easily detect and correct single faults by observing the syndrome sequence. Simulation results demonstrating the error detection and correction behavior against random s-a-0 faults are presented too.

Computer systems have evolved significantly in the last years leading to high-performance systems. This, however, has come with a cost of large power dissipation. As such, power-awareness has become a major factor in processor design. Therefore, it is important to have a complete understanding of the power and performance behavior of all processor components. In order to achieve this, the current work presents a comprehensive analysis of power-performance efficiency for different high-end microarchitecture configurations using three different workloads: multimedia, scientific, and database. The objectives of this work are: (1) to analyze and compare the power-performance efficiency for different workloads; (2) to present a sensitivity analysis for the microarchitecture parameters in order to identify which ones are more sensitive to changes in terms of power-performance efficiency; and (3) to propose power-performance efficient configurations for each workload.

The simulation results show that the multimedia workload is the one achieving the highest efficiency but the database workload is the most sensitive to parameter changes. In addition, the results also show that the parameter sensitivity depends significantly on the workload. While the issue width and clock frequency present very high sensitivity across all workloads (approximately 100%), for the database workload, the first-level instruction cache size shows an even higher sensitivity (149%). The correct configuration of these microarchitecture parameters is essential. A careless configuration of a single parameter from a baseline setup may result in a loss of the power-performance efficiency of up to 99%. Finally, carefully tuning multiple parameters simultaneously may result in gains up to 154% over the power-performance efficiency of the baseline configuration.

Residue number systems are attractive due to their basic arithmetic operations, such as addition and multiplication, are carry-free; this facilitates low-power, high-speed implementations. But converting from residue to conventional notation is generally problematic. In this paper, we propose a high-speed architecture for reverse conversion; this is based on Base Extension and the Chinese Remainder Theorem.

A novel logic family, called Split-Level Charge-Sharing Differential Logic (SCSDL), is proposed in this letter. The SCSDL uses the charge recycling technique to reduce power dissipation of differential logic in the precharge phase. The simulation results show that the SCSDL has the best power-delay product compared to several other differential logic families. An eight-bit carry lookahead adder (CLA) designed using the proposed SCSDL can reduce at least 30.64% of power-delay product compared to DCVSL CLA dissipation. A test chip was fabricated to illustrate the feasibility of the SCSDL circuit.

In this paper, a location-aided resource reservation scheme for handoff based on mobility prediction is proposed for wireless cellular networks. We analyze the performance of the proposed scheme and propose a two-dimensional random walk model for simulation. Performance evaluation is done by computing several key performance criteria, i.e., prediction accuracy, average number of reservation per call, reservation efficiency, and reservation time overhead. The influences of threshold distance, average distance where the mobile station moves along a straight line, location error and sample time are investigated, and the effectiveness of mobility prediction is also evaluated. Performance comparison reveals that the proposed scheme performs better than a solely distance-based scheme without mobility prediction.

A novel video-based finger writing virtual character recognition system (FVCRS) is described in this paper. With this FVCR system, one can enter characters into a computer by just using the movement of fingertip, without any additional device such as a keyboard or a digital pen. This provides a new wireless character-inputting method. A simple but effective background model is built for segmenting human-finger movements from cluttered background. A robust fingertip detection algorithm based on feature matching is given, and recognition of the finger-writing character is by a DTW-based classifier. Experiments show that the FVCRS can successfully recognize finger-writing uppercase and lowercase English alphabet with the accuracy of 95.3% and 98.7%, respectively.

Tracing a schematic display of an electricity distribution network is a cumbersome task and does not empower the engineer to take fast decisions to control the dynamic network because of the difficulty in reading the displayed circuits. This paper presents four different new approaches, which achieve an intelligent logical dynamically derived network connections and display for Electrical Distribution Networks. The four approaches were designed and implemented using the Object Oriented approach and programmed using Delphi graphics components. The system developed is dynamically interactive and allows switching operations as well as displays. This paper focuses on the display issues only. The logical display approaches presented in this paper eliminate the well-known difficulties of adding and retiring stations which are awkward operations in the schematic display. The four new approaches are compared in terms of speed, readability and space utilization. To our knowledge there is no similar work done previously.

In the nanometer regime, crosstalk significantly impacts the dynamic power consumption of a chip. In this paper, we present a methodology for analyzing crosstalk-induced short-circuit power dissipation in cell-based digital designs. We introduce a new cell pre-characterization technique for facilitating the estimation of crosstalk-induced short-circuit power. Examples demonstrate that the presented methodology is three orders of magnitude faster than circuit simulators while the average error is as low as 3.5%.

A full-scan structure is described, in which the classic single serial scan-path and the parallel-in/serial-out scan (PASE-Scan) designs coexist. It requires only one extra pin and a small hardware overhead with respect to the single serial scan-path approach, and is compatible with a test scheme of this type. A method for the structure design is outlined and a structure-oriented optimized procedure for obtaining the test is proposed which considerably reduces the test application cost with respect to the serial scan case, improving the previous results for parallel-serial designs. The experiments performed with the ISCAS89 benchmarks show average reductions in test length of 60.6% with respect to its full serial scan counterpart and of 58.7%, with respect to a conventional full serial scan test with normal compaction. The advantage of the COMPASES scheme in testing some circuits with multiple PASE-Scan structures is also outlined.