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COMPASES: AN OPTIMIZED DESIGN FOR TESTABILITY SCHEME TO REDUCE THE COST OF TEST APPLICATION USING PARALLEL-SERIAL SCAN DESIGN

JOSÉ M. SOLANA

Departamento de Electrónica y Computadores, Universidad de Cantabria, 39005-Santander, Spain

https://doi.org/10.1142/S0218126607003678Cited by:0 (Source: Crossref)

Abstract

A full-scan structure is described, in which the classic single serial scan-path and the parallel-in/serial-out scan (PASE-Scan) designs coexist. It requires only one extra pin and a small hardware overhead with respect to the single serial scan-path approach, and is compatible with a test scheme of this type. A method for the structure design is outlined and a structure-oriented optimized procedure for obtaining the test is proposed which considerably reduces the test application cost with respect to the serial scan case, improving the previous results for parallel-serial designs. The experiments performed with the ISCAS89 benchmarks show average reductions in test length of 60.6% with respect to its full serial scan counterpart and of 58.7%, with respect to a conventional full serial scan test with normal compaction. The advantage of the COMPASES scheme in testing some circuits with multiple PASE-Scan structures is also outlined.

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