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A full-scan structure is described, in which the classic single serial scan-path and the parallel-in/serial-out scan (PASE-Scan) designs coexist. It requires only one extra pin and a small hardware overhead with respect to the single serial scan-path approach, and is compatible with a test scheme of this type. A method for the structure design is outlined and a structure-oriented optimized procedure for obtaining the test is proposed which considerably reduces the test application cost with respect to the serial scan case, improving the previous results for parallel-serial designs. The experiments performed with the ISCAS89 benchmarks show average reductions in test length of 60.6% with respect to its full serial scan counterpart and of 58.7%, with respect to a conventional full serial scan test with normal compaction. The advantage of the COMPASES scheme in testing some circuits with multiple PASE-Scan structures is also outlined.

Test power is one of the most challenges faced by Integrated Circuits. The author proposes a general scan chain architecture called Representative Scan (RS). It transforms the scan cells of conventional scan chain or sub-chain into circular shift registers and a representative flip-flop is chosen for each circular shift register, these representative flip-flops are connected serially to setup into the RS architecture. Thus, test data shifting path is shortened, then the switching activity is reduced in the shifting operates. The proposed scan architecture has the similar test power with the multiple scan chain, and only needs same test pins with single scan chain without added test pins. The experimental results show that the proposed scan architecture achieves very low shifting power. For benchmark circuits of ISCAS89, the shifting power of the best architecture of RS is only 0.53%–13.59% of the conventional scan. Especially for S35932, the shifting power on mintest test set is only 0.53% of the corresponding conventional scan. Compared with the conventional scan, the RS only needs to add a multiplexer for each scan cells, and the hardware cost is not high.