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A full-scan structure is described, in which the classic single serial scan-path and the parallel-in/serial-out scan (PASE-Scan) designs coexist. It requires only one extra pin and a small hardware overhead with respect to the single serial scan-path approach, and is compatible with a test scheme of this type. A method for the structure design is outlined and a structure-oriented optimized procedure for obtaining the test is proposed which considerably reduces the test application cost with respect to the serial scan case, improving the previous results for parallel-serial designs. The experiments performed with the ISCAS89 benchmarks show average reductions in test length of 60.6% with respect to its full serial scan counterpart and of 58.7%, with respect to a conventional full serial scan test with normal compaction. The advantage of the COMPASES scheme in testing some circuits with multiple PASE-Scan structures is also outlined.

Usually, test pattern decompressors with dynamic reseeding are reset before starting a new test pattern decoding. The first few scan chain slices are then filled with test vectors that have lower decoding ability as the number of free variables is limited by the test access mechanism bandwidth. We have found that even within this limitation, it is possible to improve the decodability by creating fast and wide-spreading as many as possible independent linear combinations of the tester bits and using them for the scan chain loading. We evaluated features influencing the decompression quality and the hardware overhead for different decompressor principles. According to the evaluation results, we proposed a decompressor combining a XOR network and a linear feedback shift register (LFSR)-like automaton; we place the XOR network on the LFSR inputs. We demonstrate that due to this arrangement, the combined decompressor can be used without any phase shifter or state skipping ability of the LFSR. We have experimentally verified that adopting the proposed decompressor structure improves test coverage, saves the hardware resources and shortens the test application time.

Reversible circuits have been extensively investigated because of their applications in areas of quantum computing or low-power design. A reversible circuit is composed of only reversible gates and allow computations from primary inputs to primary outputs and vice-versa. In the last decades, synthesis of reversible circuits received significant interest. Additionally, testing of these kinds of circuits has been studied which included different fault models and test approaches dedicated for reversible circuits only. The analysis of testability issues in a reversible circuit commonly involves the detection of the missing gate faults that may occur during the physical realizations of the reversible gates. In this paper, we propose a design for testability (DFT) technique for reversible circuits in which the gates of a circuit are clustered into different sets and the gates from each cluster are then connected to an additional input line where, the additional line acts as an extra control input to the corresponding gate. Such arrangement makes it possible to achieve $100\%$ fault detection in any reversible circuit with a small increase in quantum cost. Experimental evaluations confirm that the proposed DFT technique incurs less quantum cost overhead with $100\%$ fault detection compared to existing DFT techniques for reversible circuits.

A new architecture of 4-bit reversible multiplier with scalability factor of order $4N$ is presented in this paper. The design procedure is based on a unique method of gates placement, which produces parity preserving circuits. This property facilitates graceful testing and full coverage of single-bit faults at lower overhead. The circuit is designed and implemented on the top of reversible analyser for obtaining operating costs in terms of number of wires, gate cost, quantum cost, garbage output and ancilla input. Testable implementation of recently reported multiplier circuits has also been performed using the existing method of testing under the same platform. This work achieved a reduction of up to 33% in operating costs when all the parameters are combined together.

March algorithms are widely used in Memory Built-In Self-Test (MBIST) on-chip memory testing, providing linear test complexities that reduce the test time and cost. However, studies show that March algorithms with complexities lower than 18N have poor coverages of faults that have emerged with the advent of the nanometer process technologies and are more relevant to nowadays memories. New March AZ1 and March AZ2 algorithms, with 13N and 14N complexities, respectively, were introduced to provide optimum coverage of those faults and to produce a shorter test than an 18N-complexity test algorithm with a lesser area overhead, thus reducing chip manufacturing costs. This paper presents the implementation and validation of MBIST controllers that applied the March AZ1 and March AZ2 algorithms in a Field-Programmable Gate Array (FPGA) device. They were implemented in the Intel Max 10 DE10-Lite FPGA Development Board. A test generator was built in FPGA, as an alternative to the external tester, to provide test vectors required in initiating the test on the memory model using the implemented MBIST. The FPGA experimental tests demonstrated that they function correctly as the expected test sequences were observed. In addition, their fault detection abilities were also validated through tests on a fault-injected memory model, which shows that the implemented March AZ1 and March AZ2 provide 80.6% and 83.3% coverage of the intended faults, respectively, which outperform any other existing 14N-complexity March algorithms.