Journal of Circuits, Systems and Computers

This paper introduces two new classes of recursive fast transforms over GF (3). They are based on recursive equations using Kronecker products that allows to obtain simple corresponding fast transforms and regular butterfly diagrams. The computational costs to calculate both classes of new transforms and the experimental results comparing introduced transforms with ternary Reed–Muller transform are also presented.

In many VLSI chips, the power dissipation of the clocking system that includes clock distribution network and flip-flops is often the largest portion of total chip power consumption. In the near future, this portion is likely to dominate total chip power consumption due to higher clock frequency and deeper pipeline design trend. Traditionally, two approaches have been used: (1) to reduce power consumption in the clock tree, several low-swing clock flip-flops and double-edge flip-flops have been introduced; (2) to reduce power consumption in flip-flops, conditional capture, clock-on-demand, data-transition look-ahead techniques have been developed. Recently, pulsed latch type flip-flops are introduced in several high-performance microprocessors to reduce E × D. In this paper, these flip-flops are described with their pros and cons. Then, a new circuit technique is described along with simulation results. The proposed pulsed latch reduces E × D by 82.6% to 95.4% compared to conventional flip-flops.

This paper presents a new translinear-C current-mode first order all-pass filter suited for high frequency operation. The new circuit offers a simpler structure than the available translinear-C works. The pole-frequency of the circuit is controllable over a wide range through external bias current of CCCII and the circuit possesses low THD for a wide range of signal amplitudes. Extensive simulations are performed to verify the utility of the proposed circuit.

This paper gives an application of exclusive-or sum-of-products (ESOP) expressions to designing cryptographic protocols. That is, this paper deals with secure computations in a minimal model, and gives a protocol which securely computes every function by means of the techniques of ESOP expressions. The communication complexity of our protocol is proportional to the size of an obtained multiple-valued-input ESOP expression. Since the historical research on minimizing ESOP expressions is now still active, our protocol will "automatically" turn to an efficient one as this research progresses. Thus, we hope that the existence of our cryptographic protocol would motivate further research on minimizing ESOP expressions.

A modified version of conditional-precharge sense-amplifier-based flip-flop (mCP-SAFF) is proposed. By using the differential clocked CMOS (C²MOS) latch with one shared output holder and the conditional-precharge modules to simplify the sense-amplifier latch, the mCP-SAFF can achieve a much shorter input to output delay (D-to-Q delay) and more symmetrical rising/falling delays than those of the original conditional-precharge sense-amplifier-based flip-flops (CP-SAFF). Post-layout simulation results show that the mCP-SAFF, compared with the widely used conventional DFF, does not suffer neither timing nor area penalties and have achieved up to 34% of power reduction ratio and 33% of power-delay-product (PDP) reduction ratio, respectively. And the mCP-SAFF is comparable to the prevailing DFFs with regard to noise immunity performance.

Digital noise generators are basic components in communication channel emulators which are used to make the test and verification of communication systems easy and fast. In this paper, a novel scheme of implementing high-speed high-probability-resolution digital AWGN generator is proposed based on a derived universal algorithm for any white f(x)-distributed noise generation. The precision and the hardware complexity of the proposed AWGN generator are discussed in detail. Implemented with FPGA, the presented AWGN generator is utilized to test a high-speed UWB communication system and performs well with excellent precision in noise probability distribution. The proposed novel scheme of implementing digital noise generators is important and helpful in building communication channel emulators to test and verify communication systems.

A fully differential third-order very high frequency (VHF) G_m–C filter based on linear transformation (LT) techniques is presented in this paper. The systematic design method and the procedure are developed to realize LT G_m–C filters efficiently. A third-order Butterworth lowpass filter embedded bandgap and bias circuits with 200 MHz cutoff frequency is implemented in the TSMC 0.18 μm 1P6M process. The total harmonic distortion (THD) of the proposed filter is - 43 dB with input signal 0.5 V_p-p and output loading capacitance 1 pF at 200 MHz. Power dissipation is 9.77 mW under 1.8 V supply voltage. Its core area occupies 0.188 × 0.186². Post simulation and experimental results that confirm the theoretical analysis are obtained. Furthermore, the proposed circuits can be extended to high-order Chebychev and elliptic filters.

This paper presents a new high speed voltage-mode MAX–MIN method for fuzzy applications. In the proposed circuits, a differential pair is employed to choose the desired input. In addition to high speed, high precision and simple expansion for multiple inputs are the main advantages of this method. HSPICE simulation results show that the proposed circuit has maximum of 1% error at 100 MHz.

In this paper, we present two new hardware architectures that implement the Smith–Waterman algorithm for DNA sequence alignment. Previous low-cost approaches based on Field Programmable Gate Array (FPGA) technology are reviewed in detail and then improved with the goal of increased performance at the same cost (i.e., area). This goal is achieved through low level optimizations aimed to adapt the systolic structure implementing the algorithm to the regular structure of FPGAs, essentially finding the optimum granularity of the systolic cells. The proposed architectures achieve processing rates close to 1 Gbps, clearly outperforming previous approaches. Comparing to the reported FPGA results of the computation of the edit-distance between two DNA sequences, throughput is doubled for the same clock frequency with a minimum area penalty. The design has been implemented on an FPGA-based prototyping board integrated into a bioinformatics system. This has allowed validating the approach in a real system (i.e., including I/O and database access), and comparing the proposed hardware solution to purely software approaches. As shown in the paper, the results are outstanding even for slow-rate buses.

The Residue Number System (RNS) is an integer system appropriate for implementing fast digital signal processors. It can be used for supporting high-speed arithmetic by operating in parallel channels without need for exchanging information among the channels. In this paper, two novel RNS are proposed. First, a new RNS system based on the modulus set {2ⁿ⁺¹, 2ⁿ - 1, 2ⁿ + 1, 2ⁿ + 2^(n+1)/2 + 1, 2ⁿ - 2^(n+1)/2 + 1}, n odd, is developed, along with an efficient implementation of its residue-to-weighted converter. The new RNS is a balanced five-modulus system, appropriate for large dynamic ranges. The proposed residue-to-binary converter is fast and hardware efficient and is based on a one's complement multi-operand adder that adds operands of size only 80% of the size dictated by the system's dynamic range. Second, a new class of multi-modulus RNS systems is proposed. These systems are based on sets consisting of two groups of moduli with the modulus product within one group being of the form 2^a(2^b - 1), while the modulus product within the other group is of the form 2^c - 1. Their RNS-to-weighted converters are based on efficient combinations of the Chinese Remainder Theorem and Mixed Radix Conversion decoding techniques. Systems based on four, five, and seven moduli are constructed and analyzed. The new systems allow efficient implementations for their RNS-to-weighted decoders, imply fast and balanced RNS arithmetic, and may achieve large dynamic ranges. The presented residue-to-weighted converters for these systems rely on simple mod(2^x - 1) hardware, which can be easily implemented as one's complement hardware.

This paper proposes a GA-based design method for two-dimensional (2D) state-space digital filters which satisfy simultaneously the magnitude response and constant group delays. The design problem of 2D state-space digital filters is formulated subject to the constraint that the resultant filters are stable. To apply the genetic algorithm to the design problem, all coefficients of 2D state-space digital filters are encoded into the Gray code representation demonstrating the superior performance to the standard binary one. In addition, a stability test routine is embedded in the design procedure in order to ensure the stability for the resultant filters. A numerical example is given to demonstrate the effectiveness of the proposed method.

Success of a tracking method depends largely on choosing the suitable window size as soon as the target size changes in image sequences. To achieve this goal, we propose a fast tracking algorithm based on adaptively adjusting tracking window. Firstly, tracking window is divided into four edge subwindows, and a background subwindow around it. Then, by calculating the spatiotemporal gradient power ratios of the target in each subwindow, four proper expansion vectors are associated with any tracking window sides such that the occupancy rate of the target in tracking window should be maintained within a specified range. In addition, since temporal changing of target is evaluated in calculating these vectors, we estimate overall target displacement by sum of expansion vectors. Experimental results using various real video sequences show that the proposed algorithm successfully track an unknown textured target in real time, and is robust to dynamic occlusions in complex noisy backgrounds.