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A SURVEY OF LOW-VOLTAGE LOW-POWER TECHNIQUES AND CHALLENGES FOR CMOS DIGITAL CIRCUITS

YU-CHERNG HUNG

Department of Electronic Engineering, National Chin-Yi University of Technology, Taichung County 411 Taiwan, R.O.C.

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SHAO-HUI SHIEH

Department of Electronic Engineering, National Chin-Yi University of Technology, Taichung County 411 Taiwan, R.O.C.

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, and

CHIOU-KOU TUNG

Department of Electronic Engineering, National Chin-Yi University of Technology, Taichung County 411 Taiwan, R.O.C.

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https://doi.org/10.1142/S0218126611007104Cited by:9 (Source: Crossref)

Abstract

Low-power design is an important research in recent years. A huge amount of papers in the open literature until now were proposed to deal with various low-power issues, including technology innovation, circuit/logic design techniques, algorithm realization, and architecture/system selection. Due to the high-energy electron effect and reliability consideration, it is necessary to further reduce the supply voltage of integrated circuit in CMOS sub-micro technologies. However, it is hard to get a whole view for various low-power low-voltage techniques in a short time. In this paper, the motivations and challenges of CMOS low-voltage low-power circuit are addressed. Various design methodologies are surveyed and summarized in whole. The paper attempts to quickly give readers a full-view conception in low-voltage low-power CMOS system design.

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