Journal of Circuits, Systems and Computers

A CMOS low quiescent current low dropout regulator (LDR) with high power supply rejection (PSR) and without large output capacitor is proposed for system-on-chip (SoC) power management applications. By cascoding a power NMOS with the PMOS pass transistor, high PSR over a wide frequency range is achieved. The gate-drive of the cascode NMOS is controlled by an auxiliary LDR that draws only 1 μA from a small charge pump, thus helping in reducing the quiescent current. Adaptive biasing is employed for the multi-stage error amplifier of the core LDR to achieve high loop gain hence high PSR at low frequency, low quiescent current at light load and high bandwidth at heavy load. A prototype of the proposed high-PSR LDR is fabricated using a standard 0.35 μm CMOS process, occupying an active area of 0.066 mm². The lowest supply voltage is 1.6 V and the preset output voltage is 1.2 V. The maximum load current is 10 mA. The measured worst-case PSR at full load without using large output capacitor is -22.7 dB up to 60 MHz. The line and load regulations are 0.25 mV/V and 0.32 mV/mA, respectively.

A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-μm CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73.19 μW under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.

This paper, presents a novel low power current mode 9 bit pipelined a/d converter. The a/d converter structure is composed of three 2.5 bit stages and one 3 bit stage operating in current mode and a final comparator which converts the analog current signal into a digital voltage signal. All the building blocks of the converter were designed in CMOS AMS 0.35 μm technology, simulated, and then a prototype converter was manufactured and measured to verify the proposed concept. The performances of the converter are compared to performances of known voltage-mode switched-capacitance and current-mode switched-current converter structures. Low power consumption and small chip area are the advantages of the proposed converter.

A low-power analogue baseband circuit for a low data-rate impulse radio ultra-wideband (IR-UWB) receiver is designed and implemented in a 0.18 μm CMOS technology, including a variable-gain amplifier (VGA), a received signal strength indicator (RSSI), and a limiting amplifier (LA). The VGA has gain range from -9 to 63 dB and bandwidth from 31 to 187 MHz. An input P1dB of -15.4 dBm is achieved at 0 dB gain. The RSSI has a dynamic range of approximately 70 dB. The RSSI linearity error is within ±1.2 dB for an input power from -77.5 dBm to -36.2 dBm. By adjusting the VGA gain and the LA threshold, the LA is able to detect an input pulse as low as 0.6 mV at a data rate of 15 mega-pulse per second (MP/s). The analogue baseband circuit draws current of 6.03 mA from a single voltage supply of 1.8 V. The test chip occupies an area of 970 μm × 750 μm, including two output buffers.

A 12-bit cyclic analog to digital converter (ADC) used in long line array infrared sensors readout circuit is presented. The architecture of a low-power amplifier shared with two groups of switched capacitors is used to reduce power consumption. By adding cross-connected switches, the amplifier's offset is effectively canceled out. The improved redundant signed digit (RSD) correction technique is employed to compensate for the error resulting from the comparator's offset in sub-ADC, and the correction technique can tolerate high level of switched capacitor mismatch error, as well. The converter manufactured with Chartered 0.35 μm CMOS process exhibits 0.92 LSB maximum differential nonlinearity (DNL) and 1.5 LSB maximum integral nonlinearity (INL). The ADC has a 69.3 dB signal to noise and distortion ratio (SNDR) at 250 kS/s sample rate and 3 MHz clock frequency. It dissipates 0.8 mW with 3.3 V supply and occupies 0.22 × 0.9 mm².

A front-end read-out application specific integrated circuit (ASIC) for a multichannel pixel X-Ray detector system has been fabricated and tested. The chip provides signal amplification for pixelated compound semiconductors such as Cadmium Telluride (CdTe) and Cadmium Zinc Telluride (CZT) with either 1 mm or 200 μm pitch. Both the detector (compound semiconductor) and ASIC are combined to target future research applicable to spectroscopic imaging in high intensity X-Ray biomedical detector systems. The ASIC was fabricated in a 0.35 μm process by Austria Microsystems and consists of 32 channels, where each channel contains a charge-sensitive amplifier, a pulse shaper and two further stages of amplification providing an overall gain of 1 mV per kilo electron volt (keV) for photons within the energy range of 30–120 keV. The preamplifier and shaper circuits are designed for both positive and negative charge collection (electrons and holes) produced by the CdTe or CZT detectors. The ASIC's shaper has been designed with a time constant of 100 ns to allow operation at photon rate events above 1 Million photons per pixel per second. The design and characterization of the readout chip will be discussed in this paper presenting results from both the simulated and the fabricated chip.

Low-power design is an important research in recent years. A huge amount of papers in the open literature until now were proposed to deal with various low-power issues, including technology innovation, circuit/logic design techniques, algorithm realization, and architecture/system selection. Due to the high-energy electron effect and reliability consideration, it is necessary to further reduce the supply voltage of integrated circuit in CMOS sub-micro technologies. However, it is hard to get a whole view for various low-power low-voltage techniques in a short time. In this paper, the motivations and challenges of CMOS low-voltage low-power circuit are addressed. Various design methodologies are surveyed and summarized in whole. The paper attempts to quickly give readers a full-view conception in low-voltage low-power CMOS system design.

This paper presents circuit-based approaches to SIMPL Systems (SIMulation Possible, but Laborious Systems), which could be regarded as a "public-key" version of Physical Unclonable Functions. The use of these systems can help us to avoid some of the potential vulnerabilities of conventional cryptography, such as its dependency on secret binary keys. Two specially designed circuits for SIMPL systems are discussed: "skew" memories and massively parallel analog processor arrays known as Cellular Nonlinear Networks. We argue that these circuits are able to serve as SIMPL systems in practice, and discuss their security against numerical and physical attacks.

Multi-threshold voltage CMOS (MTCMOS) is the most widely used circuit technique for suppressing the subthreshold leakage currents in idle circuits. When a conventional sequential MTCMOS circuit transitions from the sleep mode to the active mode, significant bouncing noise is produced on the power and ground distribution networks. The reliability of the surrounding active circuitry is seriously degraded. A dynamic forward body bias technique is proposed in this paper to alleviate the ground bouncing noise in sequential MTCMOS circuits without sacrificing the data retention capability. With the new dynamic forward body bias technique, the peak ground bouncing noise is reduced by up to 91.70% as compared to the previously published sequential MTCMOS circuits in a UMC 80 nm CMOS technology. The design tradeoffs among important design metrics such as ground bouncing noise, leakage power consumption, active power consumption, data stability, and area are evaluated.

The scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to total power dissipations. This paper presents two flip-flops based on dual-threshold CMOS and multiple leakage reduction techniques to reduce their leakage dissipations. In the DT-TG FF (Dual-Threshold Transmission Gate Flip-Flop), some transistors on non-critical paths use high-threshold devices to reduce their leakage currents, while the other transistors on critical paths use low-threshold devices to maintain performance. The MLRT FF (Multiple Leakage Reduction Technique Flip-Flop) uses P-type CMOS techniques, MTCMOS (Multi-Threshold CMOS) power-gating and dual-threshold technique to reduce both sub-threshold and gate leakage dissipations. Taken as an example, a practical sequential system realized with the two low-leakage flip-flops is demonstrated using a mode-5 × 5 × 5 counter. The simulation results show that the two flip-flops achieve considerable leakage reductions.