No Access

FAST ALGORITHMS FOR THERMAL-AWARE FLOORPLANNING

LIN WANG

School of Statistics, Capital University of Economics and Business, Beijing 100070, P. R. China

https://doi.org/10.1142/S0218126614500984Cited by:6 (Source: Crossref)

Abstract

Thermal-aware floorplanning is an effective way to solve the thermal problem in modern integrated circuit (IC) designs. Existing thermal-aware floorplanning methods are all based on simulated annealing (SA), genetic algorithms (GAs) or linear programming (LP), which are quite time-consuming. In this paper, we propose two fast algorithms for thermal-aware floorplanning, a greedy algorithm based on the less-flexibility-first (LFF) principle and a hybrid algorithm combining the greedy algorithm and an SA-based refinement. The greedy algorithm can fast obtain a locally optimized floorplan with reduced area and temperature. The hybrid method can get similar results compared with pure SA-based approaches but it is still much faster.

This paper was recommended by Regional Editor Emre Salman.

Keywords:

References

T.-C. Chen and Y.-W. Chang , IEEE Trans. Comput.-Aided Des. Integrated Circ. Syst. 25 , 637 ( 2006 ) . Crossref, Web of Science, Google Scholar
P. Sassone and S.-K. Lim , IEEE Trans. Comput. Aided Des. Integrated Circ. Syst. 25 , 1075 ( 2006 ) . Crossref, Web of Science, Google Scholar
C.-R. Li , W.-K. Mak and T.-C. Wang , IEEE Trans. Very Large Scale Integration (VLSI) Syst. 21 , 523 ( 2013 ) . Crossref, Web of Science, Google Scholar
J. Yan and C. Chu , IEEE Trans. Comput. Aided Des. Integrated Circ. Syst. 32 , 175 ( 2013 ) . Crossref, Web of Science, Google Scholar
D. Abdullahet al., VLSI floorplanning design using clonal selection algorithm, 2013 Int. Conf. Informatics, Electronics Vision (ICIEV) (2013) pp. 1–6. Google Scholar
E. Ardestaniet al., Enabling power density and thermal-aware floorplanning, 2012 28th Annual IEEE Semiconductor Thermal Measurement and Management Symp. (SEMI-THERM) (2012) pp. 302–307. Google Scholar
J. Cong, J. Wei and Y. Zhang, A thermal-driven floorplanning algorithm for 3D ICs, IEEE/ACM Int. Conf. Computer Aided Design, 2004. ICCAD-2004 (2004) pp. 306–313. Google Scholar
M. Healyet al., Thermal optimization in multi-granularity multi-core floorplanning, Design Automation Conf. 2009. ASP-DAC 2009. Asia and South Pacific (2009) pp. 43–48. Google Scholar
W. L. Hunget al., Interconnect and thermal-aware floorplanning for 3D microprocessors, 7th Int. Symp. Quality Electronic Design, 2006. ISQED '06 (2006) pp. 98–104. Google Scholar
A. Jain et al. , Comput. Digital Tech. IET 5 , 169 ( 2011 ) . Crossref, Web of Science, Google Scholar
S. Logan and M. Guthaus, Fast thermal-aware floorplanning using white-space optimization, 17th IFIP Int. Conf. Very Large Scale Integration (VLSI-SoC) (2009) pp. 65–70. Google Scholar
V. Nookala, D. Lilja and S. Sapatnekar, Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis, Proc. 2006 Int. Symp. Low Power Electronics and Design, 2006. ISLPED'06 (2006) pp. 298–303. Google Scholar
L. Qi, Y. Xia and L. Wang, Simulated annealing based thermal-aware floorplanning, 2011 Int. Conf. Electronics, Communications and Control (ICECC) (2011) pp. 463–466. Google Scholar
P.-H. Wu and T.-Y. Ho, Thermal-aware bus-driven floorplanning, Int. Symp. Low Power Electronics and Design (ISLPED) 2011 (2011) pp. 205–210. Google Scholar
L. Xiaoet al., Fixed-outline thermal-aware 3D floorplanning, Design Automation Conf. (ASP-DAC), 2010 15th Asia and South Pacific (2010) pp. 561–567. Google Scholar
S. Kirkpatrick , C. D. Gelatt Jr. and M. P. Vecchi , Science 220 , 671 ( 1983 ) . Crossref, Web of Science, Google Scholar
N. Graciaet al., Thermal aware modern VLSI floorplanning, 2012 Int. Conf. Devices, Circuits and Systems (ICDCS) (2012) pp. 187–190. Google Scholar
W. L. Hunget al., Thermal-aware floorplanning using genetic algorithms, Sixth Int. Symp. Quality of Electronic Design, 2005. ISQED 2005 (2005) pp. 634–639. Google Scholar
J. H. Holland , Adaptation in Natural and Artificial Systems ( MIT Press , Cambridge , 1992 ) . Crossref, Google Scholar
H. Williams, Logic and Integer Programming (Springer, Berlin, 2009) pp. 25–68. Crossref, Google Scholar
D. Cuestaet al., 3D Thermal-aware floorplanner for many-core single-chip systems, Test Workshop (LATW), 2011 12th Latin American (2011) pp. 1–6. Google Scholar
M. Healyet al., Microarchitectural floorplanning under performance and thermal tradeoff, Proc. Design, Automation and Test in Europe, 2006. DATE '061 (2006) pp. 1–6. Google Scholar
Y.-C. Changet al., B*-trees: A new representation for non-slicing floorplans, Proc. 2000 Design Automation Conf. 2000 (2000) pp. 458–463. Google Scholar
W. Huanget al., Differentiating the roles of IR measurement and simulation for power and temperature-aware design, ISPASS (2009) pp. 1–10. Google Scholar
S. Donget al., Module placement based on quadratic programming and rectangle packing using less flexibility first principle, Proc. 2004 Int. Symp. Circuits and Systems, 2004. ISCAS '045 (2004) pp. 61–64. Google Scholar
S. Weiet al., On handling the fixed-outline constraints of floorplanning using less flexibility first principles, IEEE Int. Symp. Circuits and Systems, 2006. ISCAS 2006. Proc. (2006) pp. 5595–5598. Google Scholar
S. Donget al., VLSI block placement using less flexibility first principles, Design Automation Conf. 2001. Proc. ASP-DAC 2001. Asia and South Pacific (2001) pp. 601–604. Google Scholar
MCNC Benchmark Netlists for Floorplanning and Placement, Available at http://lyle.smu.edu/manikas/Benchmarks/MCNC_Benchmark_Netlists.html . Google Scholar
Y. Liuet al., A hierarchical approach for incremental floorplan based on genetic algorithms, Proc. First Int. Conf. on Advances in Natural Computation (2005) pp. 219–224. Google Scholar