Journal of Circuits, Systems and Computers

Nowadays time-to-digital converter (TDC) is the most popular method of time measurement in many applications. The CMOS process, which gains an advantage over Emitter Coupled Logic (ECL) and GaAs in cost and portability, provides sufficient space for TDC development. This paper presents a review of CMOS TDCs classified by circuit topologies and performance. For each TDC structure, the principle exposition and performance analysis are given in detail. Moreover, a comparison among all kinds of TDCs mentioned in this paper is presented in tabular form. Finally, we discuss the obstacle to the development of TDC and the possible tendency for future work in summary.

"Vedic mathematics" is the ancient methodology of mathematics which has a unique technique of calculations based on 16 "sutras" (formulae). A Vedic squarer design (ASIC) using such ancient mathematics is presented in this paper. By employing the Vedic mathematics, an (N × N) bit squarer implementation was transformed into just one small squarer (bit length ≪ N) and one adder which reduces the handling of the partial products significantly, owing to high speed operation. Propagation delay and dynamic power consumption of a squarer were minimized significantly through the reduction of partial products. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using 90-nm CMOS technology. The propagation delay of the proposed 64-bit squarer was ~ 16 ns and consumed ~ 6.79 mW power for a layout area of ~ 5.39 mm². By combining Boolean logic with ancient Vedic mathematics, substantial amount of partial products were eliminated that resulted in ~ 12% speed improvement (propagation delay) and ~ 22% reduction in power compared with the mostly used Vedic multiplier (Nikhilam Navatascaramam Dasatah) architecture.

This paper describes an analysis of multi-stage and multi-rate IIR switched capacitor (SC) decimators using an interactive switched capacitor multi-rate compiler (ISCMRATE). Motivated by the experimental observations, the purpose of this paper is to explore a portion of characteristics for the multi-stage IIR SC decimators, with their implications in the context of a complete IIR SC filter.

To overcome the limitations of conventional multi-stage IIR SC decimators, a novel solution has been introduced for the implementation of a multi-stage IIR SC circuit. Based on the statistical approach of the compiler, we provide the comparative analysis for different IIR SC decimators, including total capacitor area, capacitance spread and arbitrary anti-aliasing amplitude responses with a decimating factor in single and multi-stage building blocks. Examples are given to illustrate the practical feasibility of this compiler.

Localization and tracking technology based on received signal strength indicator (RSSI) is one of the most popular topics because of its low demand on hardware and cost. But the complexity of the indoor environment, leads to the uncertainty of the radio propagation which can seriously affect the positioning accuracy based on the received signal strength. Focused on the wall reflection in the indoor environment, the radio propagation characteristic based on ray-tracing model is analyzed and one strategy for the near wall localization is presented. The actual hardware platform and experimental test results show the applicability of the empirical logarithmic path loss model for localization and the effect of the wall reflection.

Development in VLSI design allows multi- to many-cores to be integrated on a single microprocessor chip. This increase in the core count per chip makes it more critical to design an efficient memory sub-system especially the shared last level cache (LLC). The efficient utilization of the LLC is a dominant factor to achieve the best microprocessor throughput. Conventional set-associative cache cannot cope with the new access pattern of the cache blocks in the multi-core processors. In this paper, the authors propose a new design for LLC in multi-core processor. The proposed v-set cache design allows an adaptive and dynamic utilization of the cache blocks. Unlike lately proposed design such as v-way caches, v-set cache design limits the serial access of cache blocks. In our paper, we thoroughly study the proposed design including area and power consumption as well as the performance and throughput. On eight-core microprocessor, the proposed v-set cache design can achieve a maximum speedup of 25% and 12% and an average speedup of 16% and 6% compared to conventional n-way and v-way cache designs, respectively. The area overhead of v-set does not exceed 7% compared to n-way cache.

To solve the problem that it is difficult to install isolation resistors across each output port, a new five-way microstrip Wilkinson power divider with double-layer topology is developed. The isolation resistors are placed on the second substrate by using half-wavelength microstrip transmission lines with the introduction of Archimedean spirals to reduce the circuit size. To demonstrate the design method, a five-way equal power divider is designed; its size is optimized at the center frequency of 2.45 GHz. The fabricated sample has been tested. Measured results are in good agreement with simulations.

This paper presents a current mode step-up/step-down DC–DC converter with high efficiency, small output voltage ripple, and fast transient response. The control scheme adaptively configures the converter into the proper operation mode. The efficiency is improved by reducing the switching loss, wherein the converter operates like a buck or boost converter, and conduction loss, wherein the average inductor current is reduced in transition modes. The output voltage ripple is significantly reduced by incorporating two constant time transition modes. A fast line transient response is achieved with small overshoot and undershoot voltage. An adaptive substrate selector (ASS) is introduced to dynamically switch the substrate of PMOS power transistors to the highest on-chip voltage. A lossless self-biased current sensor with high-speed and high-accuracy is also achieved. The proposed converter was designed with a standard 0.5 μm CMOS process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V. The maximum load current is 600 mA, and the maximum efficiency is 94%. The output voltage ripple is less than 15 mV in all operation modes.

Thermal-aware floorplanning is an effective way to solve the thermal problem in modern integrated circuit (IC) designs. Existing thermal-aware floorplanning methods are all based on simulated annealing (SA), genetic algorithms (GAs) or linear programming (LP), which are quite time-consuming. In this paper, we propose two fast algorithms for thermal-aware floorplanning, a greedy algorithm based on the less-flexibility-first (LFF) principle and a hybrid algorithm combining the greedy algorithm and an SA-based refinement. The greedy algorithm can fast obtain a locally optimized floorplan with reduced area and temperature. The hybrid method can get similar results compared with pure SA-based approaches but it is still much faster.

Although parallel multipliers are optimal for speed, they occupy considerable chip area. For applications with lengthy operands as cryptography, the required area grows further. On the other hand, digit multipliers reduce chip area at the expense of the number of cycles required to complete the multiplication. In such multipliers, one-or-both inputs are received serially one digit per cycle. Digit multiplier designs are flexible with respect to the digit width enabling designers to select the most suitable compromise between area and cycle count for the application under consideration. This paper proposes a new digit serial–serial multiplier that is more area efficient compared to other functionally-similar multipliers.

First, we propose a new unsigned digit serial–serial multiplier that is area efficient. The multiplier has the ability to handle unequal-width operands. That is, one operand can be of dynamic width (unlimited digit count) and the other operand is of fixed width. Moreover, with a small modification, the multiplier can operate on two's complement operands. Then, the design is extended to support bit-level pipelining: the critical path of the multiplier pipeline stage is independent of the operand width and the digit width. Simulation results show that the proposed multiplier reduces the area over similar multipliers by up to 28% and reduces power by up to 31%.

The wireless sensor networks (WSNs) are formed by a large number of sensor nodes working together to provide a specific duty. However, the low energy capacity assigned to each node prompts users to look at an important design challenge which is lifetime maximization. Especially the availability of nodes, the sensor coverage, and the connectivity have been included in discussions on network lifetime. Therefore, designing effective techniques that conserve scarce energy resources is a critical issue in WSNs. In this regard, we are interested in developing various mechanisms to save energy based on the constraints involved for energy consumption in WSNs. Three mechanisms are proposed to reduce the number of control packets responsible for path discovery, optimize diffusion area, and balance the load distribution in the network.

In this paper, a new mixed mode full-wave rectifier which consists of a current differencing transconductance amplifier (CDTA), resistor and two complementary MOS transistor is presented. The proposed circuit is called as mixed mode because it can be used as current-, voltage-, transimpedance- and transconductance-mode rectifier depending on how the resistor is connected to the input or output of the circuit. The presented circuit has an appropriate zero crossing performance, linearity, low component count, and can be adapted to modern IC technologies. It is also suitable for monolithic integrated implementation. LTSPICE simulations with 0.18 μm CMOS model obtained through TMSC are included to verify the workability of the proposed circuit. We also performed noise and Monte Carlo analyses. Various simulation results are presented to show the effectiveness of the proposed circuit.

This paper presents a transadmittance-mode (TAM) universal biquad filter with independently electronic tunability. The proposed biquad filter only employs three operational transconductance amplifiers (OTAs) and two grounded capacitors which are the minimum components count necessary for realizing independently electronic tunability of the parameters ω₀ and ω₀/Q without the need of control factors matching conditions. Moreover, the proposed circuit still achieves nearly all of the main advantages: (i) simultaneous realizations of universal filtering responses (low-pass, high-pass, band-pass, band-reject and all-pass) from the same topology, (ii) versatile input/output functions, (iii) orthogonally electronic tunability of the parameters ω₀ and Q without the need of control factors matching conditions, (iv) no need of any resistors, (v) cascadable feature for all input and output terminals, (vi) no need of extra inverting or non-inverting amplifiers, (vii) the employment of only grounded capacitors, (viii) no component-value constraints (except for allpass filter function) and (ix) low active and passive sensitivity performances. H-spice simulations with TSMC 0.35 μm 2P4M CMOS process technology validate theoretical predictions.

In this study, active and passive control techniques are applied for the synchronization of two identical Vilnius chaotic oscillators. The differential equations of Vilnius oscillator are described according to its circuit model. Based on Lyapunov function, the active and passive controllers are used to realize the synchronization of Vilnius chaotic systems. Numerical simulations are presented to verify and compare the effectiveness of proposed control techniques.

In this paper, an ultra-low-voltage gain-enhanced four-phase charge pump is proposed. The proposed charge pump is designed in 0.18 μm 1.8 V standard CMOS process with high voltage boosting efficiency when the supply voltage is between 0.5 V and 1.8 V. Moreover, it eliminates the body effect by means of adding two auxiliary substrate switching PMOS transistor. The simulation results show that the proposed charge pump has higher efficiency than the other two low voltage charge pumps when the resistive load is 100 M ohm and the supply voltage is between 0.5 and 1.8 V. A test chip has been realized in a 0.18 μm 1.8 V standard CMOS process. The test results show perfect performance when the supply voltage is between 0.7 and 1.8 V. The proposed charge pump is quite suitable for low power applications.

As networks-on-chips (NoCs) are expected to provide the necessary scalable communication medium for future many-core systems-on-chips (SoCs) optimizing their resources is of great importance. What is really needed is an efficient NoC architecture with optimized resources that requires very little customization by the SoC developers. One of the most important area and power hungry resources is the NoC's buffers. In this work, a new Modified Fat Tree (MFT) NoC architecture with buffers engineered for maximum efficiency (performance versus area) is presented. Extensive simulations are used to show optimum buffer design/placement under different conditions of traffic types and NoC sizes.