Journal of Circuits, Systems and Computers

To extend the existing knowledge on first-order voltage-mode all-pass filters, this paper presents two novel first-order voltage-mode all-pass sections, each employing single fully differential second-generation current conveyor (FDCCII) being used as the newly obtained fully differential voltage conveyor (FDVC), a resistor and a grounded capacitor. Both the proposed circuits possess high-input and low-output impedance feature, which makes the proposed circuits ideal for voltage-mode systems. Non-ideal study along with simulation results is given for validation.

In this research paper, we propose an automatic segmentation method of multispectral magnetic resonance image (MRI) of the human brain using an information fusion approach through the framework of the possibility theory. The fusion process is summarized into three essential steps. First, a data is extracted from the various images and modeled in a common mathematical framework, in this step the fuzzy C-means (FCM) algorithm is chosen. The combination rule is used to combine this information in the second step. A final segmented image is the result of the last phase. Our experimental results using simulated brain MRI datasets show that the proposed approach overcome the impact of the noise and substantially improve the accuracy of image segmentation.

In this paper, the design of an ASIC is presented that implement a low-cost system for the supervision of water quality in urban areas or rivers. Photo catalytic sensor (PCS) estimates the parameter biological oxygen demand (BOD) which is generally used to estimate quality of water. The system proposed in this paper involves a simple potentiometric approach that provides a correlation in the input–output signals of low-cost sensors. This approach which is more users friendly and fast in operation is obtained by modeling and optimization of sensor for water quality monitoring. This is to overcome several drawbacks generally found in the previous flow injection analysis method of determining chemical oxygen demand (COD)-like complex designing, nonlinearity and long computation time. The system constitutes a significant cost reduction in the supervision of water quality monitoring. The main reason of employing a readout circuit to PCS circuitry, is the fact that the fluctuation of O₂ influences the threshold voltage, which is internal parameter of the FET and can manifest itself as a voltage signal at output but as a function of the trans-conductance gain. The trans-conductance is a passive parameter and in order to derive voltage or current signal from its fluctuations the sensor has to be attached to readout circuit. This circuit provides high sensitivity to the changes in percentage of O₂ in the solution. In this design simple potentiometric approach with few passive components are used to build a readout circuit. The paper focuses on the electronic implementation of the readout system for the PCS which optimize the circuit performance and increases reliability.

This paper presents the design, implementation and performance evaluation of the linear processor array accelerator for matrix multiplication. We call it matrix multiplication processor (MMP). The MMP is composed of n processing elements (PEs) connected in a chain, distributed memory, and dedicated address generator unit (AGU) to generate memory addresses. By using this approach, address generation does not increase the processing time. The AGU is one major difference in the proposed architecture compared to graphics processing units (GPUs) that use ALUs to create addresses. MMP is based on FPGA technology since this circuits possess extreme degree of parallelism and ability to customize the RAM and data path architecture to the computation. We have considered performance metrics of the proposed architecture in the sense of number of PEs, execution time, speedup, efficiency and gain factor. We have implemented AGU and PE in Xilinx Spartan 2E FPGAs using ISE 9.01 as a software tool. We compare our design with respect to the execution time, number of PEs, AT measure, speedup and efficiency with other solutions proposed in the literature.

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing satellites and space systems. Unfortunately, these devices are extremely sensitive to various kinds of unwanted effects induced by space radiations especially single-event upsets (SEUs) as soft errors in configuration memory. To face this challenge, a variety of soft error mitigation techniques have been adopted in literature. In this paper, we describe an area-efficient multiplier architecture based on SRAM-FPGA that provides the self-checking capability against SEU faults. The proposed design approach, which is based on parity prediction, is able to concurrently detect the SEU faults. The implementation results of the proposed architecture reveal that the average area and delay overheads are respectively 25% and 34% in comparison with the plain version while the conventional duplication with comparison (DWC) architecture imposes 117% and 22% overheads. Moreover, the single and multi-upset fault injection experiments reveal that the proposed architecture averagely provides the failure coverage of 83% and 79% while the failure coverage of the duplicated structure is 85% and 84%, respectively for SEU and MEU faults.

In this paper, closed-form models for the computation of finite ramp responses of current-mode resistance inductance capacitance (RLC) interconnects in VLSI circuits are presented. These models are based on extended Eudes model and Scaling and Squaring algorithm which allow numerical estimation of delay in lossy very large scale integration (VLSI) interconnects. The existing Eudes model for interconnect transfer function approximation is extended to higher-order and then Scaling and Squaring method is applied for further improving the accuracy of delay estimation. With the equivalent lossy interconnect transfer function, finite ramp responses are obtained and line delay is estimated for various line lengths, per unit inductances and load capacitances. The estimated 50% delay values are compared with HSPICE W-element model. The worst case errors observed in the estimated delay values are 14.3% for Eudes model and 2% for extended Eudes model while the proposed Scaling and Squaring based model with 1% error is in very good agreement with HSPICE for line lengths 0.1–0.5 cm. The estimated crosstalk induced delay values of proposed model maximum error percentage is nearly half of the extended Eudes model. For both single and three coupled interconnect lines, the proposed model is in good agreement with HSPICE.

A novel design procedure for a compact multilayer bandpass filter is proposed and examined. The filter is realized using quasi-lumped multilayer resonators. Based on the orientation of these coupled-resonator pairs, a second-order bandpass filter is realized with transmission zeros. In order to achieve a low external quality factor, i.e., a wider filter bandwidth, different types of feeder realization are considered. The design methodology with all relevant steps is presented and the equivalent-circuit of the resonator is also derived and verified. The filter design is simulated using a 3D electromagnetic model and validated by measurements on the fabricated filter. The simulation and experimental results are in good agreement.

This paper presents three current-mode quadrature oscillator (QO) circuits based on dual-output current differencing transconductance amplifier (DO-CDTA) which is designed from block diagram. The proposed circuits consist of two DO-CDTAs and two grounded capacitors. The circuits can provide two sinusoidal output currents with 90° phase difference. The condition of oscillation (CO) can be adjusted independently from the frequency of oscillation (FO) by adjusting the bias currents of the DO-CDTA. The proposed circuits have high output impedance appropriate for cascade connection application in current mode which is capable to directly drive load. The circuits use only grounded capacitors without any external resistor which is very appropriate for further development into an integrated circuit. Moreover, the oscillator circuits can also adjust amplitude of the output signal. The results of PSPICE simulation program are corresponding to the theoretical analysis.

Based on the achievements of realization of the light dependent resistor (LDR) memristor (MR) analog model, a chaotic system has been proposed in this paper. The construction of such a nonlinear system is firstly shown in this paper, by dissipative characteristic analysis, equilibrium point and stability analysis, the strange attractor is possibly existing at each equilibrium point is confirmed. Also the dynamic characters are discussed, which indicates the nonlinear circuit we built based on LDR MR is a chaotic system.

A new two-stage method of finite state machines (FSMs) synthesis for PAL-based complex programmable logic devices (CPLD) is proposed. It is based on both the wide fan-in of PAL cells and existence of the classes of pseudoequivalent states of Moore FSM. The first step targets decreasing for the number of PAL cells used for implementing the block of input memory functions. The second step targets decreasing for the number of PAL cells in the block of microoperations. An example of application of the proposed method is given, as well as results of experiments carried out for standard benchmarks.

In this paper, we extend the topological formulae of Maxwell and Kirchhoff, characterizing the non-singularity of node-admittance and loop-impedance matrices, to mixed problems, that is, to circuits combining admittance and impedance descriptions or, in nonlinear cases, involving both voltage- and current-controlled resistors. By means of this mixed formula we analyze the index of differential-algebraic models of nonlinear uncoupled circuits in a very broad setting, namely, without assumptions on their topology, their passivity or the controlling variables for nonlinear resistors. In particular, our approach allows for a characterization of index two circuits in topologically degenerate settings, which had been so far elusive in the non-passive context. As a byproduct we address the unique solvability of mixed resistive circuits, a problem which also arises in connection to the so-called DC-solvability condition of dynamic circuits. For the sake of brevity, we discuss in less detail how to extend the analysis to problems with mixed descriptions in reactive devices.

In this paper, we present a low-voltage tunable active filter for microwave applications. The proposed filter is based on a single-transistor active inductor (AI), that allows the reduction of circuit area and power consumption. The three active-cell bandpass filter has a 1950 MHz center frequency with a -1 dB flat bandwidth of 10 MHz (Q ≈ 200), a shape factor (30–3 dB) of 2.5, and can be tuned in the range 1800–2050 MHz, with constant insertion loss. A dynamic range of about 75 dB is obtained, with a P1dB compression point of -5 dBm. The prototype board, fabricated on a TLX-8 substrate, has a 4 mW power consumption with a 1.2 V power supply voltage.

In this paper, a Multi-layered configurable logic block (CLB) unit for field programmable gate arrays (FPGAs) is proposed based on quantum-dot cellular automata (QCA) technology. The design is made in multiple layers which help to process information simultaneously, in different layers. Various components of CLB like (4 × 16) Decoder, Memory units, Multiplexers and RS-Flip flops are all designed in multiple layers using higher input majority gates to reduce the cell count and latency compared to previous designs. QCA Designer tool is used to design and simulate the model. The Coherence vector approximation is used for obtaining simulation results.

A 13-bit analog-to-digital converter (ADC) is designed in 0.35 μm CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 μm technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm–0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply.

Fast and accurate estimation of soft error rate in VLSI circuits is an essential step in a soft error tolerant ASIC design. In order to have a cost effective protection against radiation effects in combinational logics, an accurate and fast method for identification of most susceptive gates and paths is needed. In this paper, an efficient, fast and accurate method for soft error propagation probability (SEPP) estimation is presented and its performance is evaluated. This method takes into account all three masking factors in multi cycles. It also considers multiple event transients as a new challenge in soft error tolerant VLSI circuit design. Compared with Monte Carlo (MC) simulation-based fault injection method, our SEPP estimation method has a high level of accuracy (with less than 2% difference) while offering 1000× speedup as compared with MC-based simulation.