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A LOW POWER 13-BIT 50MS/s RECIRCULATING PIPELINE ANALOG TO DIGITAL CONVERTER

ARASH ESMAILI

Microelectronics Research Center, Urmia University, Urmia 57159, Iran

Corresponding author.

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HADISEH BABAZADEH

Microelectronics Research Center, Urmia University, Urmia 57159, Iran

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KHAYROLLAH HADIDI

Microelectronics Research Center, Urmia University, Urmia 57159, Iran

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, and

ABDOLLAH KHOEI

Microelectronics Research Center, Urmia University, Urmia 57159, Iran

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https://doi.org/10.1142/S021812661450090XCited by:2 (Source: Crossref)

Abstract

A 13-bit analog-to-digital converter (ADC) is designed in 0.35 μm CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 μm technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm–0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply.

This paper was recommended by Regional Editor Piero Malcovati.

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