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In a field effect diode, carriers of a p–n junction can be modulated on-line. The p and n regions are created by two oppositely biased, and closely spaced, gates in CMOS SOI technology. Using gates as the third terminal, the field effect diode can operate as a switch or as an amplifying element. In this paper, a conventional differential comparator is designed and its performance is compared with a circuit which uses field effect diodes in its output stage. It is shown that the large current sinking and supplying capability of the field effect diode causes this comparator to operate faster than the conventional circuit, consumes less power and covers less chip area.

A 13-bit analog-to-digital converter (ADC) is designed in 0.35 μm CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 μm technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm–0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply.

This paper presents a novel low-voltage rail-to-rail comparator circuit and derives optimal transistor size ratios for both conventional latch-based and the proposed comparators which operate in transistor subthreshold region. The obtained analytical results serve well as guidelines for designing low-voltage comparators and the proposed circuit is significantly faster than existing rail-to-rail comparator designs in ultra-low voltage operation.

Low-power circuits are highly in demand in this power-hungry world of batteries and portable devices. Though many low-power techniques are prevalent at various stages of a VLSI design cycle, but most of them have retained their own domain. A novel, digital-in-concept, fully differential voltage comparator circuit has been implemented in this paper. This provides substantial reduction in the power consumption. It is highly cost-effective, both in terms of time and efforts as an analog circuit is being designed on digital basis. The proposed voltage comparator has been designed and simulated in Cadence${}^{\circledR }$ Virtuoso Analog Design Environment using UMC 180nm CMOS technology at 1.8V supply.

This paper describes a standard cell-based new approach of comparator design for flash ADC. Conventional flash ADC comparator consumes up to 60% of the power due to resistive ladder network and analog comparators. Threshold inverter quantized (TIQ) comparators reported earlier have improved speed and provide low-power, low-voltage operation. But they need feature size variation and have non-linearity issues. Here, a new standard cell comparator is proposed which retains all advantages of TIQ comparator and provides improved linearity with reduced hardware complexity. A 4-bit ADC designed using the proposed comparator requires 206 minimum-sized transistors and provides large area saving compared to previously proposed designs. Thermometer code is partitioned using algebraic division theorem. This conversion is used for mathematical modeling and complexity reduction of decoder circuit using semi-parallel organization of comparators. Circuit is designed using 90 nm technology which exhibits satisfactory performance even in process variation.

A 12-bit 350MS/s ADC with 75dB SFDR fabricated in 0.18$\mu$m SiGe BiCMOS process is presented. To improve the power efficiency, the ADC employs a novel residue amplifier (RA) by exploiting the hetero-junction bipolar transistor (HBT). We also propose a fast comparator to save time for the residue settling of pipeline stages. A fully integrated reference buffer with “negative bootstrap power” (NBP) is proposed to improve both high power supply rejection ratio (PSRR) and ground supply rejection ratio (GSRR). A bandgap reference (BGR) with ultra-low leakage current start-up loop is also presented. The measured results show that with Nyquist input, the SFDR achieves 75dB and 63dB SNDR up to 350MS/s and consumes 180mW (only ADC core) with 580fj/cov Waldon FOM.

In this paper, a comparator and an operational amplifier considered as essential components, constituting a 10-bit 50-MHz pipeline Analog-to-Digital Converter for Wireless Local Area Network (WLAN) applications, are described and designed. All post-layout and Monte-Carlo simulations, using a 0.35$\mu$m CMOS AMS process technology with $3.3$V supply voltage and an input common-mode range of $1.15–2.15$V, are achieved. An improved clocked comparator with a dynamic latch, based on a switched capacitor network, using the current reuse technique for slew rate enhancement and positive feedback for offset voltage compensation, is presented. The operational amplifier, consisting of a fully differential folded cascode operational transconductance amplifier, providing high-gain and good stability, is exhibited. A new frequency compensation technique, based on active resistors, is used to improve amplifier phase-margin. The Monte-Carlo performance results of the designed clocked comparator provide an offset voltage of $32.32$mV with $2.49$mV 3$\sigma$ deviation, a slew rate of $8.29$V/ns with $0.45$V/ns 3$\sigma$ deviation, and a propagation delay of $4.16$ns with $0.15$ns 3$\sigma$ deviation. Monte-Carlo performance results of the designed operational amplifier provide a phase-margin of $63.01^{\circ }$, and a high-gain of $79.22$dB with $1.92^{\circ }$ and $4.86$dB 3$\sigma$, respectively, by using $1\text{pF}$ load capacitance.

In this paper, a novel and simple multi-bit quantizer based on the threshold inverter quantization (TIQ) approach is presented for use in sampled-data circuits. The key part is a front-end signal conditioning circuit with the aid of the interpolation technique that makes it possible to realize a rail-to-rail input range operation over the conventional threshold inverter-based quantizer circuits while maintaining the benefits of the TIQ structure without employing any analog-intensive circuits such as current sources or amplifiers, thus achieving a digital-compatible implementation. Simulation results in TSMC 90-nm CMOS technology at a power-supply voltage of 1V confirm the efficient performance of the proposed circuit.

Application-Specific ICs (ASIC) are manufactured in bulk for a long time. In this paper, an approach to High-Speed Application-Independent IC (HS-AIIC) design is discussed. A resolution-selective (RS) and resolution-adaptive (RA) 8-bit Flash ADC are designed for use in various high-speed applications. With the choice of resolution, one can work with the trade-off between speed, power consumption, and resolution for a particular application. The proposed resolution selection algorithm can be implemented for any set of resolutions for a flash ADC design. Further, an adaptive block is added to make the ADC design adaptive in nature so that we do not have to select a particular resolution manually. The proposed design entrusts on saving manufacturing cost and increases the functionality of ADC on a single chip. Proposed resolution adaptive 8-bit flash ADC design dissipates 512mW of power with an ENOB of 7.56 bits and SNDR of 46.27dB for 1GHz sampling clock pulse.

This paper presents the implementation of a sense amplifier for a low-power cardiac pacemaker using the Differential Voltage Current Conveyor (DVCC). Two significant aspects of the pacemaker are sensing and pacing. The pulse generator, which is the heart of the pacemaker, consists of a sense amplifier, a logic unit and a timing control unit. The sense amplifier comprises an instrumentation amplifier, a bandpass filter and a comparator that are used to detect the QRS complex wave from the cardiac signal. Based on the output of a sense amplifier, the logic unit and the timing control unit decide whether to pace the heart or not, which achieves the requirement of the demand pacing. In this paper, a novel design of the sense amplifier using a DVCC is proposed, and the simulations are performed using 130-nm TSMC technology. Furthermore, the modes of the pacemaker VVI, DDD and rate-responsive algorithms have been implemented using the structural approach in VHDL by taking into consideration the timing cycles of a pacemaker. The design analysis shows that the proposed model of pacemaker is highly efficient and consumes significantly less energy.

An operational trans-conductance amplifier (OTA) is a fundamental component of electronic appliances. This paper introduces a novel design of OTA for minimal power, low voltage applications. The proposed OTA comprises an ultra low power current mirror design with enhanced bandwidth. The proposed OTA circuit is operated at 0.8V, contributing input noise of 26.33nV/(Hz)${}^{1/2}$ with a power of $29.52\mu$W. The additional parameters of new OTA are DC gain (87.32dB), common mode rejection ratio (145.47dB), gain bandwidth (4.73MHz), phase margin (36.56${}^{\circ }$). These figures are significantly improved as compared to conventional OTAs. Analog-to-digital convertor (ADC) is also designed as an application of the proposed OTA. The improvements offered by ADC in terms of power and bandwidth are also compared with state of the art.

This paper presents the realization of binary and floating-point comparators on FPGA. The implementation is done by exploiting the primitive instantiation of FPGA resources which has enabled a significant improvement in resource utilization in terms of Look-Up Table (LUT) usage and overall combinational path delay when compared to the conventional inference approach. The comparator architectures are implemented using Vivado 2020.1 and ISE Design Suite 14.7 environment on multiple Xilinx FPGA platforms and are compared with the existing designs. The results indicate an improvement of 33.33% and 45.45% in LUT utilization, 14.41% and 30.73% in delay for 32-bit and 64-bit binary comparators respectively, compared to the existing architectures. The proposed floating-point comparator requires 88.57% and 285.29% lesser LUTs for single precision and double precision representation respectively, compared to the existing design.

TOAD or Tera Hertz Optical Asymmetric Demultiplexer is an optical switch. Using this switch, we have invented an optical comparator. This optical comparator circuit is very simple in structure with a higher speed (200 Gbps) and finds useful application in optical computation and communication network system. We have simulated all three outputs in detail and shown the eye diagram of all three outputs of the optical comparator. We found high values of extinction ratio (ER), contrast ratio (CR), and quality factor (Q value) for the three outputs of the comparator.

Several attempts have been made to reconcile a number of rival theories on the role of the hippocampus in long-term memory. Those attempts fail to explain the basic effects of the theories from the same point of view. We are reviewing the four major theories, and shall demonstrate, with the use of mathematical models of attention and memory, that only one theory is capable of reconciling all of them by explaining the basic effects of each theory in a unified fashion, without altogether sacrificing their individual contributions. The key issue here is whether or not a memory trace is ever stored in the hippocampus itself, and there is no reconciliation unless the answer to that question is that there is not. As a result of the reconciliation that we are proposing, there is a simple solution to several outstanding problems concerning the neurobiology of memory such as: consolidation and reconsolidation, persistency of long term memory, novelty detection, habituation, long-term potentiation, and the multifrequency oscillatory self-organization of the brain.

We propose and analyze a “spintronic/straintronic” reconfigurable equality bit comparator implemented with a nanowire spin valve whose two contacts are two-phase multiferroic nanomagnets and possess bistable magnetization. A reference bit is “written” into a stable magnetization state of one contact and an input bit in that of the other with electrically generated strain. The spin-valve’s resistance is lowered (raised) if the bits match (do not match). Multiple comparators can be interfaced in parallel with a magneto-tunneling junction to determine if an $N$-bit input stream matches an $N$-bit reference stream bit by bit. The system is robust against thermal noise at room temperature and a 16-bit comparator can operate at $\sim 743$MHz while dissipating $\sim$28fJ per cycle. This implementation is more energy-efficient than CMOS-based implementations and the reference bits can be stored in the comparator itself without the need for refresh cycles or the need to fetch them from a remote memory for comparison. That improves reliability, speed and security.