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A 13-bit analog-to-digital converter (ADC) is designed in 0.35 μm CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 μm technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm–0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply.

Data converters play a key role in modern analog/mixed-signal systems. Accordingly, it is important to investigate their performance and yield under uncertain parameters over the design process. An efficient approach for automatic design and yield enhancement of data converters is presented. The proposed algorithm generates a general netlist for each data converter and improves transistor sizing to reach acceptable values for performance parameters with an evolutionary process, and finds the best yield simultaneously. The applied framework on two data converter structures demonstrates a reliable circuit with optimum performance, power consumption, and area overhead over a single evolutionary process in 0.18$\mu$m technology.