Journal of Circuits, Systems and Computers

This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply.

Low noise amplifier (LNA) is an important component in RF receiver front end. An inductively degenerated cascode low noise amplifier (IDCLNA) is mostly preferred for producing good trade-offs such as high gain, low noise figure (NF), high reverse isolation and low power consumption for narrowband applications. This IDCLNA structure is also used to reduce the gate induced noise on the noise performance by inserting the capacitance in parallel with the gate-to-source capacitance of main transistor. Usually, the parasitic overlap capacitances can impose serious constraints on achievable performance and is taken into account in IDCLNA. In this paper, IDCLNA is designed at a frequency of 2.4 GHz with analyzing the impact of parasitic overlap capacitances on IDCLNA in terms of unity current gain frequency (f_T) which will affect the NF of IDCLNA and simulated using 130 nm, 90 nm and 65 nm CMOS technologies. The NF of IDCLNA with and without parasitic overlap capacitances are analyzed and compared for different short channel CMOS processes. Simulation results show that the parasitic overlap capacitances have advantageous to reduce the gate induced noise in IDCLNA for 130-nm CMOS process for 2.4 GHz applications.

This paper presents the design and implementation of a 11-bit 160 MSPS analog-to-digital converter (ADC) for next generation super high-speed wireless local area network (WLAN) application. The ADC core consists of one front sample and hold stage and four cascades of 2.5 bit pipeline stages with opamp sharing between successive stages. To achieve low power dissipation at 1.2 V supply, a single stage symmetrical amplifier with double transimpedance gain-boosting amplifier is proposed. High speed on-chip reference buffer with replica source follower is also included for linearity performance. The ADC was fabricated in a standard 130-nm CMOS process and an occupied silicon area of 0.95 mm × 1.15 mm. Performance of 73 dB spurious-free-dynamic-range is measured at 160 MS/s with 1 Vpp input signal. The power dissipation of the analog core chip is only 50 mW from a 1.2 V supply.

In this paper, we present, at transistor level, a very low complexity Gaussian monocycle pulse generator/modulator for DPSK low voltage and low power tunable ultra-wideband (UWB) applications. The pulse generator, simulated in a SMIC 0.13 μm CMOS technology, provides a tunable, both in pulse width duration and repetition time, Gaussian monocycle compliant with the sub-GHz ETSI band and suitable to be used in UWB radio applications. The preliminary IC simulation results show a pulse duration from 1 ns up to 20 ns with good pulse symmetry and with the DPSK modulation capability. The circuit power consumption is about 1 mW from a 1.8 V power supply.

Since the last two decades, the trend of device miniaturization has increased to get better performance with a smaller area of the logic functions. In deep submicron regime, the demand of fabrication of nanoscale Complementary metal oxide semiconductor (CMOS) VLSI circuits has increased due to evaluation of modern successful portable systems. Leakage power dissipation and reliability issues are major concerns in deep submicron regime for VLSI chip designers. Power supply voltage has been scaled down to maintain the performance yield in future deep submicron regime. The threshold voltage is the critical parameter to trade-off the performance yield and leakage power dissipation in nanoscaled devices. Low threshold voltage improves the device characteristics with large leakage power in nanoscaled devices. Several leakage reduction techniques at different levels are used to mitigate the leakage power dissipation. Lower leakage power increases the reliability by reducing the cooling cost of the portable systems. In this article, we are presenting the explanatory general review of the commonly used leakage reduction techniques at circuit level. We have analyzed the NAND3 gate using HSPICE EDA tool for leakage power dissipation at different technology nodes in active as well as standby modes. Process, voltage and temperature effects are checked for reliability purpose. Our comparative results and discussion of different leakage reduction techniques are very useful to illustrate the effective technique in active and standby modes.

This paper presents a novel optimal utilization of hybrid wind–solar system as dynamic voltage restorer (DVR) for voltage sag, voltage swell, outage and unbalanced voltage mitigation. Besides the voltage regulation, the proposed DVR reduces the energy consumption from the three phase utility grid by utilizing the rated inverter capability after excessive or equal real power generation to the load demand during both day time and night time. It reduces the energy consumption from the three phase utility grid. However, the reduction of energy consumption is always desirable for the reduction of panel tariff and electricity demand. The proposed system was simulated using MATLAB-SIMULINK in which the input parameters were selected from the metrological data of the selected location to validate the advantage of the proposed system.

This paper presents an asynchronous instruction cache memory for average-case performance, rather than worst-case performance. Even though the proposed instruction cache design is based on a fixed delay model, it can achieve high throughput by employing a new memory segmentation technique that divides cache memory cell arrays into multiple memory segments. The conventional bit-line memory segmentation divides a whole memory system into multiple segments so that all memory segments have the same size. On the contrary, we propose a new bit-line segmentation technique for the cache memory which consists of multiple segments but all the memory segments have the same delay bound for themselves. We use the resister-capacitor (R-C) modeling of bit-line delay for content addressable memory–random access memory (CAM–RAM) structure in a cache in order to estimate the total bit-line delay. Then, we decide the number of segments to trade-off between the throughput and complexity of a cache system. We synthesized a 128 KB cache memory consisting of various segments from 1 to 16 using Hynix 0.35-μm CMOS process. From the simulation results, our implementation with dividing factor 4 and 16 can reduce the average cache access time to 28% and 35% when compared to the non-segmented counterpart system. It also shows that our implementation can reduce the average cache access time by 11% and 17% when compared to the bit-line segmented cache that consists of the same number of segments that have the same size.

An attempt is made for simplifying the circuit structure of the surge protective device (SPD) installed on single-phase AC power supply lines of electronic systems. In the light of the drawback of the traditional circuit, a simplified circuit is proposed. The simplified circuit can substantially reduce the number of the protective components and the size of the SPD chassis. In order to compare the protective performances between the traditional and simplified circuits, an impulse experimental arrangement is built to measure their residual voltages. The measured results show that the voltage protection level of the simplified circuit is the same as that of the traditional circuit. Therefore, replacement of the traditional circuit by the simplified circuit is really feasible in lightning overvoltage protection of AC power supplies of electronic systems.

A high-speed and high-accuracy continuous-time common-mode feedback block (CMFB) is presented. To satisfy speed and accuracy requirements, some modifications have been applied on differential difference amplifier (DDA) CMFB circuit. The proposed method is applied to a folded cascode op-amp with power supply of 3.3 V. In order to verify the proposed circuit, simulations are done in 0.35 μm standard CMOS technology. In the worst condition when the output common-mode (CM) voltage is initialized to VCC or GND, only 1.1 ns is required to set the output CM voltage on the desired level. Also in a wide range of input CM voltage variations, the deviation of the output CM voltage from reference voltage is less than 6 mV, so simulation results confirm the expected accuracy and speed while simultaneously the proposed CMFB circuit preserves other characteristics of DDA CMFB circuit such as unity gain frequency, 3-dB bandwidth, phase margin and linearity.

Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-amplifier based flip-flop (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed flip-flop operating with energy recovery single phase sinusoidal clock shows better performance. The proposed flip-flop also reduces the leakage current and glitch.

Increasing temperatures of the processing elements (PEs) on VLSI may threaten the reliability and performance of a hard real-time system. This paper presents a temperature-aware algorithm to reconfigure two-dimensional VLSI arrays in the presence of faulty PEs. Based on dynamic programming, the proposed algorithm constructs each logical column with the lowest temperature for a cool target array on a given processor array. In addition, the lower bound of the temperatures of the cool target array has been established. Simulation results show that the temperatures of target array are reduced without loss of harvest in comparison to the state-of-the-art. Moreover, the produced peak temperature of cool target array is pretty close to the lower bound.

Multicore designs have become the dominant organization for future high performance microprocessors. Instead of increasing cache sizes, clock frequencies, pipeline depths or register file (RF) ports, multicore designs tend to make each processor core simple but highly efficient. This new dimension for improving performance and power efficiency in multicore requires us to rethink processor architecture. Multiply-accumulate (MAC) operation is such a performance improvement technique that needs to be reviewed. MAC operation is the fundamentals of many DSP and multimedia applications, but it tends to be awkward to implement in an orthogonal instruction set architecture (ISA) because of operand bandwidth problem, instruction encoding problem, and hardware cost problem. So a big question is that whether we should support MAC or not in high-efficiency processor designs? This paper does a comparative study on this question and introduce data bandwidth relaxing techniques to eliminate narrow bandwidth provided by two-port RFs. The trade-off are also made to solve the instruction coding and hardware cost problem. So, the new design wisdom becomes that if you support multiply (MUL) operation, then support MAC operation.

In order to achieve higher compression performance the fidelity range extension (FRExt) amendment was added to the H.264 advanced video coding (AVC) standard. It uses both 4 × 4 and 8 × 8 integer discrete cosine transform (DCT) adaptively in the high profiles. This led to additional complexity of the initial version of the H.264/AVC encoder which had substantially high computational complexity. In this paper, we propose a new algorithm which reduces the computational complexity for software implementation of horizontal 8 × 8 integer DCT by more than 25%. Simulation results indicate 22% reduction in the computation time by using the proposed algorithm.

In this paper, a new phonetic alphabet called PUNJARPAbet for speech processing in the Punjabi language has been designed. The new phonetic coding scheme PUNJARPAbet developed in this paper has been primarily designed to encode the text and speech corpora recently developed by the authors in the Punjabi language. This recently developed corpus has at least 20 special features. PUNJARPAbet is capable of coding examples related to all special features of the new corpus. PUNJARPAbet is an all upper-case coding scheme and is consistent with the all upper-case version of the famous coding scheme ARPAbet developed by the Advanced Research Projects Agency (ARPA). The new scheme is very easy to follow, and is the most suitable scheme for typing on an ordinary computer keyboard as well as an ordinary typewriter. Unlike many other schemes such as the famous International Phonetic Alphabet (IPA), the PUNJARAbet is free from the laborious, irritating, and time-consuming necessities for dealing with the special symbols. It has been clearly demonstrated in this paper that PUNJARPAbet is a versatile, efficient and convenient coding scheme for not only the Punjabi language, but also any language which has sounds similar to the ones found in the Punjabi speech.

An efficient method for rectangular boundary extraction from aerial image data is proposed in this paper. A centroid neural network (CNN) with a metric utilizing line segments is adopted to group low-level line segments for detecting rectangular objects. The proposed method extracts rectangular boundaries for building rooftops from 3D edge images with various types of noises arising from the stereo matching process. In order to overcome the noises in 3D edge images including line segments of shadows, a clustering method utilizes the constraint where the heights of building rooftops are similar and the clustering process is performed with candidate 3D line segments with similar heights. Experiments are performed with a set of high-resolution satellite image data. The results show that the proposed method can remove noisy segments including shadow lines efficiently and thus find more accurate rectangular boundaries and building information.

A novel 1/4-rate clock phase detector (PD) structure for phase locked loop (PLL)-based clock and data recovery (CDR) is proposed. In this topology, the retimed data is generated within the circuit and no extra circuit is required. Furthermore, the error and reference signals are independent of delay time through gates and thus, no extra replica circuit is needed to compensate such delay. Designed in a 0.18-μm CMOS technology, the proposed 10 Gb/s PD consumes 30 mA from a 1.8 V supply, resulting in a lower power consumption for high-speed applications compared to conventional topologies.

In this paper, a model-order reduction (MOR) technique with the advantage of critical frequency preservation capability is proposed using the particle swarm optimization (PSO). The new approach is capable of simplifying single-input single-output (SISO) systems as well as multi-input multi-output (MIMO) systems. If critical frequency preservation is desired, then this objective is achieved by retaining the exact critical frequencies of the full-order model as a subset in the reduced-order model. Otherwise, the reduction process is proceeded without such restriction. The reduction process is performed using the PSO technique to determine all of the necessary parameters in the reduced model. Determining the reduced-order model is performed based on minimizing the mean square error between the outputs of the original full-order model and the outputs of the reduced model. For method evaluation and validation, the proposed technique was applied to different models and compared with some of the well-known methods and recently published work for MOR. Results' comparison shows clearly the superiority of the proposed technique in terms of quality performance and accuracy of substructure preservation.

In this study, a multistage fault-tolerant (MSFT) scheme for two fixed-width array multipliers is proposed. To tolerate the fault that occurs in an integrated circuit, an architecture by using three redundant triple module redundancy (TMR) processing elements (PEs) (TMR-PE) is proposed. The proposed Type-I MSFT multipliers divide the array multiplier into multiple stages, and implement a single PE by considering multiple computation cycles to achieve a low area design. Thus, the MSFT multiplier employs the TMR-PEs to achieve a low-cost fault-tolerant design. The TMR-PEs were designed using compressors with multiple operands, such as 4-2 compressors or other compressors with additional operands, to reduce the number of computation cycles and expedite the execution process. To improve the fault-correction capability, Type-II MSFT multipliers that follow the multistage structure, which was designed as a TMR technique, were proposed. Because of implementation using a 0.18-μm CMOS process, the long word-length MSFT multiplier saves a substantial amount of the circuit area. The proposed 64 × 64 Type-I MSFT multiplier has only 13% of the circuit area and 3% of the delay overhead of the original multiplier. Based on the measurements of the area-delay product (AT) metric, the value of the 64 × 64 Type-I MSFT multiplier is only 0.21-fold of the value of the original multiplier. Regarding the fault-correction capability, the 64 × 64 Type-II MSFT multiplier achieves an area-delay-fault efficiency (ATF) that is 11-fold of the value of the original TMR multiplier.

A very simple, wide range and programmable pulse width controller or duty cycle corrector (DCC) is presented. Simulating the circuit in 0.35 μm Complementary MOSFET (CMOS) technology shows that the frequency range of the input signal can be within 250 MHz to 1.6 GHz, with a duty cycle of 30–70%. The proposed circuit generates an output signal with programmable duty cycle in the range of 30–70% with steps of 10% which could be extended to more steps by simple variations. The systematic peak-to-peak jitter at center frequency (1 GHz) is 1ps, while adding a random noise source of 5% of the power supply, increases it to 13 ps. the power consumption at maximum speed (1.6 GHz) is 4.9 mW. Monte Carlo simulations show maximum of 3.4% error at the 1.5 GHz input frequency and 70% output duty cycle.

A digital communication channel must have linear-phase characteristic such that the transmitted signal will keep its waveform unchanged after the signal transmission. However, since the actual communication channels usually possess nonlinear phase, it is necessary to connect a phase-linearizing circuit (phase-circuit) to such a nonlinear phase channel for linearizing the whole phase characteristic. In this paper, we propose a new iterative optimization scheme that utilizes the second-order-cone-programming (SOCP) for designing a high-accuracy phase-circuit. By approximating the highly nonlinear design constraint as a second-order-cone (SOC) constraint, a phase-circuit can be successfully designed through iterating the SOCP scheme. As compared to other existing linear-programming (LP) design and SOCP design, this new iterative SOCP-based minimax design can further reduce the peak errors of the frequency response and phase response of the designed phase-circuit. As a consequence, the new design method can further improve the phase-circuit design accuracy. We will utilize two design examples to verify the performance improvements over other existing design techniques.