Journal of Circuits, Systems and Computers

In an attempt to reduce exhaust emissions from transportation vehicles, the Taiwanese government plans to enact the "no idling emission" policy regarding motorcycles/scooters. Automatic Idling Stop and Go (AISG) technology is a simple low cost method in which the internal combustion engine is automatically powered off when the scooter stops and restarted when the driver wishes. However, due to dissimilarities between scooters and automobiles in terms of driving behavior and powertrain configuration, the AISG topology and control strategy as used in automobiles cannot be applied to scooters directly. This paper investigated the feasibility of applying the AISG control technique to scooters to enhance the system's security and reliability and address public concerns about AISG by analyzing riding behavior and security issues. The goal of this study was to demonstrate an AISG device, which included the development of a miniaturized AISG control module and control logic algorithm considering operative convenience and safety. Finally the developed AISG control module was installed in a four-stroke, electronic-fuel-injection (EFI) scooter, enabling us to perform an actual on-road test to verify the feasibility and reliability of the AISG control technology.

The research into series connection of dc–dc converters has been concentrating more recently on creating a high voltage low current string. However, the interleaving technique of series-connect photovoltaic (PV) module integrated converters (MICs) has not been sufficiently addressed so far. This paper proposes a low cost high performance interleaving technique based on series PV MICs to reduce the output voltage-ripples. With the reduced voltage-ripples, the size and cost of capacitors at grid connected inverters can be reduced. The proposed technique is capable of solving the problem for PV panels with mismatched operating conditions. Each PV panel is able to track its own maximum power point (MPP) which simultaneously delivers the maximum power for the system. The proposed technique is mathematically investigated based on boost (step-up) converters and validated by Simulink/Matlab simulation and experiment results. The MPP tracking (MPPT) algorithm is tested for a PV/battery charging system with satisfactory performances in both steady-state and transient responses with reduced voltage-ripples.

Studying blocks behavior during their lifetime in cache can provide useful information to reduce the miss rate and therefore improve processor performance. According to this rationale, the peLIFO replacement algorithm [M. Chaudhuri, Proc. Micro'09, New York, 12–16 December, 2009, pp. 401–412], which learns dynamically the number of cache ways required to satisfy short-term reuses preserving the remaining ways for long-term reuses, has been recently proposed. In this paper, we propose several changes to the original peLIFO policy in order to reduce the implementation complexity involved, and we extend the algorithm to a shared-cache environment considering dynamic information about threads behavior to improve cache efficiency. Experimental results confirm that our simplification techniques reduce the required hardware with a negligible performance penalty, while the best of our thread-aware extension proposals reduces average CPI by 8.7% and 15.2% on average compared to the original peLIFO and LRU respectively for a set of 43 multi-programmed workloads on an 8 MB 16-way set associative shared L2 cache.

Class-D amplifier features very high efficiency on power delivery because its switching operation consumes tiny static power on very low on-resistance. In this work, a multilevel technique is presented to improve total-harmonic-distortion (THD) and signal-to-noise-ratio (SNR) of pulse-width-modulation (PWM) filterless class-D amplifiers. The proposed method consists of a multilevel converter and a time division adder (TDA) followed by PWM modulator. The PWM-modulated signal is arranged into several time divisions and then integrated and encoded to a set of parallel control signals for multilevel converter. Instead of the two-level PWM signal, the output signal of a multilevel converter is as stairway with less transient variation. The performance of THD and SNR are therefore improved because the instantaneous variation of signal is greatly reduced. To demonstrate the proposed method, a filterless audio amplifier was implemented by TSMC 5 V–0.35 μm CMOS technology. With 8 Ω speaker and 550 mW maximum power, experiment results show that the THD, SNR and power efficiency can be achieved over 0.02%, 85 dB and 85%, respectively.

This paper presents a voltage-controlled oscillator (VCO) with automatic amplitude control (AAC) loop. The proposed AAC VCO employs a hybrid type AAC loop and targets the Industrial, Scientific and Medical (ISM) band applications. The proposed AAC loop can also prevent the AAC from generating extra noise to the VCO and avoid stability problem which is common for conventional AAC loop. Detail transient analysis of this AAC VCO is derived. Based on this analysis, design steps applicable for such type of AAC loop is obtained. Measurement result shows the peak amplitude variation over the operation range of 2.25–2.54 GHz is less than 9 mV (without the AAC loop, amplitude variation can be as large as 40 mV, or 22.2% for 180 mV amplitude). Power consumption of the proposed AAC VCO is 4.5 mW while the power consumed by the loop is 0.8 mW and phase noise is -105 dBc/Hz at 100 kHz offset frequency. Worst case settling time is less than 10.5 μs.

In the semiconductor manufacturing process, fault detection which aims at constructing a decision tool to maintain high process yields is a major step of the process control. Unfortunately, the class imbalance in the modern semiconductor industry makes feature selection for fault detection quite challenging. However, the characteristic has usually been ignored in the open literatures. This paper analyzes the challenge and indicates some of the reasons are due to the dataset shift, the small samples and the class overlapping caused by the class imbalance. To cope with the problems, a new feature selection approach is proposed, which combines the global and local resampling and named ensemble manifold sensitive margin fisher analysis (EMSMFA). Our approach consists of three key components: (1) At the global level, the bagging-based ensemble model is used to overcome the overfitting caused by the data shift; (2) At the local level, the manifold-based oversampling named the weighted synthetic minority oversampling technique (WSMOTE) is proposed to solve the small samples problem in the minority class; (3) The sensitive margin fisher analysis (SMFA) is used to solve the challenge caused by the class overlapping. The proposed fault detection method is demonstrated through its application to the semiconductor wafer fabrication process. The experimental results confirm the EMSMFA improves the performance of fault detection.

Clock distribution has been a major limitation on delay, power and routing resources in ultra-large nanoscale circuits. Some emerging technologies are proposed to use RF instruments for on-chip clock routing in large chips but they suffer from large power and area overheads. In this paper, a hybrid radio frequency (RF) and metal clock networking architecture corresponding with an efficient RF and metal clock routing is presented which combines the benefits of RF/wireless interconnect and metal/wired connections to reach a reasonable trade-off between RF and metal interconnect technologies. Our experiments show that clock network delay and clock tree congestion is improved by 61% and 40% on average. Moreover, sensitivity of attempted benchmarks to process variation of interconnects is reduced considerably. These improvements are gained at a cost of less than 2% of area overhead and less than 10% power consumption overhead for large circuits. It is shown that overheads are very small for large circuits such that this technology will be completely feasible and reasonable for too large and complex circuits.

Nowadays high-performance computing (HPC) architectures are designed to resolve assorted sophisticated scientific as well as engineering problems across an ever intensifying number of HPC and professional workloads. Application and computation of key trigonometric functions sine and cosine are in all spheres of our daily life, yet fairly time consuming task in high-performance numerical simulations. In this paper, we have delivered a detailed deliberation of how the micro-architecture of single-core Itanium^® and Alpha 21264/21364 processors as well as the manual optimization techniques improve the computing performance of several mathematical functions. On describing the detailed algorithm and its execution pattern on the processor, we have confirmed that the processor micro-architecture side by side manual optimization techniques ameliorate computing performance significantly as compared to not only the standard math library's built-in functions with compiler optimizing options but also Intel^® Itanium^® library's highly optimized mathematical functions.

This paper proposes a framework, which requires keeping tracks of both logical I/O access operations and their corresponding physical access on the storage servers in a parallel file system, to build a self-tuning storage system. Thus, the built self-tuning storage system is able to support dynamical data migrating and data pre-fetching transparently from the view point of clients to boost I/O performance. To this end, we first devised an approach to find out the pairs of logical I/O operations and their associated physical I/O operations. We then employed working set modeling to form I/O access patterns and their corresponding disk access patterns. Finally, with the information about existing access patterns and the similarity analysis of access patterns, it is not difficult to predict the future I/O access operations for possible I/O optimization. Through a series of experiments based on several realistic benchmarks, we show that the newly proposed self-tuning storage system is capable of enabling data migration and data pre-fetching dynamically by using the information about I/O access patterns and the predicted future I/O operations. Therefore, it can improve I/O data throughput significantly for the applications with complicated access patterns; especially, for the applications that require to process multiple-dimensional data, such as medical image processing applications and geographic information system (GIS) applications.

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) with high static and dynamic linearity is proposed. Compared to traditional intrinsic-accuracy DACs, the static linearity is obtained by a series of subsidiary DACs which can shorten the calibration cycle with smaller additional circuits. The presented DAC is based on the segmented architecture and layout has been carefully designed so that better synchronization among the current sources can be achieved. The DAC is implemented in a standard 0.18-μm CMOS technology and the current source block occupies less than 0.5 mm². The measured differential nonlinearity (DNL) and integral nonlinearity (INL) performance is ± 0.3 LSB and ± 0.5 LSB, respectively, and the spurious free dynamic range (SFDR) is 75 dB at 1 MHz signal frequency and 200 MHz sampling frequency.

Field programmable gate array (FPGA) implemented array of Duffing oscillators for weak signal detection in noisy environments is presented in this paper. The array of Duffing oscillators is an efficient method for detecting weak signals with unknown exact frequency and phase delay. Because of the high computation resource requirement, especially for online weak signal detection, hardware implementation is a proper solution. In this FPGA implementation, the array was constructed using multiprocessor Nios II system. In the proposed multiprocessor system, each oscillator was implemented by a separate Nios II processor. Also, a separate Nios II processor was dedicated to control and detect the state of other oscillators. The proposed system was implemented using one of the Altera's Cyclone IV GX FPGAs. In this paper, beside the structure and resource utilization of the array of oscillators, an experimental result was also presented in order to show effectiveness of the implementation.

An important aspect of the real-time image processing applications using orthogonal moments is the speed of their computation. They can be computed directly or via geometric moments (GMs). One of the fast methods to generate GMs is the usage of the cascaded digital filter outputs. However, a concern of this design is that the outputs of the digital filters, which operate as accumulators, increase exponentially as the orders of moment increase. It is shown in previous works, for an N × N image, the digital filter outputs are sampled at N or later instances. In this paper, we propose a new formulation to solve this problem by using a set of lower digital filter output values as the order of moments increases. This is achieved by sampling the digital filter outputs at earlier instances, N, N - 1, N - 2,…,N - p, where p is the maximum moment order. This method enables the usage of the lower digital filter output values for higher-order moments. As the moment order approaches N, the number of additions is approximately 45% less for the proposed method when compared with the existing methods, resulting in a corresponding reduction in computation time.

We present the integration and accuracy and power improved hearing aid system that proposes the triple oscillation-based loops (TOL) technique. Compared with the conventional techniques, the technique replaces the interface capacitors, A/D and D/A convertors with the oscillation-based closed loop and the calibration/operation feedback paths, which are able to enhance the integration of the system and improve the system's accuracy and power performance. Specifically, the technique achieves the only once of the second-order delta-sigma modulation with an integrator and an oscillator. To realize the architecture, the current mode blocks with calibration and successive subtraction are presented on the circuit design. Simulated with a 0.13 μm standard CMOS process in Cadence, with the 16 ohm loudspeaker impedance under the 1 V supply voltage, the input referred DC offset voltage with interface capacitor free is achieved below 2.5 mV; and the signal-to-noise and distortion rate (SNDR) achieves 50 dB@400 mV_p-p output voltage. Moreover, the power consumption with no load is maintained within 350 μW.