Journal of Circuits, Systems and Computers

Initially introduced as special-purpose accelerators for graphics applications, graphics processing units (GPUs) have now emerged as general purpose computing platforms for a wide range of applications. To address the requirements of these applications, modern GPUs include sizable hardware-managed caches. However, several factors, such as unique architecture of GPU, rise of CPU–GPU heterogeneous computing, etc., demand effective management of caches to achieve high performance and energy efficiency. Recently, several techniques have been proposed for this purpose. In this paper, we survey several architectural and system-level techniques proposed for managing and leveraging GPU caches. We also discuss the importance and challenges of cache management in GPUs. The aim of this paper is to provide the readers insights into cache management techniques for GPUs and motivate them to propose even better techniques for leveraging the full potential of caches in the GPUs of tomorrow.

This paper investigates the problem of angle estimation for bistatic multiple-input multiple-output (MIMO) radar with non-uniform linear arrays, and proposes an improved spectrum searching generalized estimation of signal parameters via rotational invariance techniques (ESPRIT) algorithm for joint direction of departure (DOD) and direction of arrival (DOA) estimation algorithm in bistatic MIMO radar. The proposed algorithm obtains initial estimation of angles obtained from the signal subspace, and uses the 1D local searchings to achieve the joint estimation of DOD and DOA. Compared to the spectrum searching generalized-ESPRIT algorithm which requires the global searchings and additional pairing, the proposed algorithm just needs the local searchings and obtains automatically paired 2D angle estimation. The angle estimation performance of the proposed algorithm is almost the same as that of the generalized-ESPRIT algorithm, and better than ESPRIT-like algorithm. Furthermore, the proposed algorithm is suitable for irregular array geometry, has much lower complexity than the spectrum searching generalized-ESPRIT algorithm, and imposes less constraint on the transmit/receive sensor spacing, which need not be limited to a half-wavelength strictly. The simulation results verify the effectiveness of the algorithm.

This paper presents an approach to the design of a high-precision CMOS voltage reference. The proposed circuit is designed for TSMC 0.35 μm standard CMOS process. We design the first-order temperature compensation bandgap voltage reference circuit. The proposed post-simulated circuit delivers an output voltage of 0.596 V and achieves the reported temperature coefficient (TC) of 3.96 ppm/°C within the temperature range from -60°C to 130°C when the supply voltage is 1.8 V. When simulated in a smaller temperature range from -40°C to 80°C, the circuit achieves the lowest reported TC of 2.09 ppm/°C. The reference current is 16.586 μA. This circuit provides good performances in a wide range of temperature with very small TC.

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal oxide semiconductor field effect transistor (MOSFET), VGOT MOSFET and fin field effect transistor (FinFET) as sleep transistor reduces the sub-threshold leakage current by 45.529%, 47.265% and 86.431%, respectively, when compared with inverter in absence of sleep transistor. This proves substantial improvement as compared to the planar CMOS inverter. Further, these techniques applied for a two input NAND gate resulted in reduction of leakage current by 20.536%, 23.955% and 99.942%, respectively.

This paper presents a systematic process for designing a damping controller for pulse width modulated series compensator (PWMSC) to improve the angular stability of a multi-machine power system. The proposed controller is robust and tuned by satisfying the multiple H_∞ performance criteria to stabilize the system at multiple operating conditions. The design problem has been converted into a constrained nonlinear optimization problem with the time domain-based objective function which is solved by an augmented Lagrangian particle swarm optimization (ALPSO) algorithm. The proposed control scheme has been implemented on two nonlinear test systems. The nonlinear simulation results clearly verify that the designed controller with proposed model improves the dynamic stability of the case studies, particularly when the operating loadings changes.

In this paper, a 1 mm × 1 mm fully integrated wideband dual-stage power amplifier (PA) for long-term evolution (LTE) band 1 (1920–1980 MHz) is presented. Fabricated in a 2 μm InGaP/GaAs hetero-junction bipolar transistor (HBT) process, the operating gain is observed to be 31.3 dB. The PA meets the minimum adjacent channel leakage ratio (ACLR) requirement of -30 dBc for LTE with 20 MHz wide channel bandwidth up to an output power of 30 dBm with the aid of a novel dual stage linearizer. Biased at low quiescent current of less than 100 mA with a headroom consumption of 3.5 V, the power added efficiency (PAE) is observed to be 38.29% at 30 dBm. With this high linear output power, the stringent requirement of antenna path loss is nullified. PA serves to be the first reported work to achieve 30 dBm linear output power at supply voltage of 3.5 V.

Multiple clock domain (MCD) systems have different blocks/IP cores operating at different frequencies. These different clocks are generated from a high frequency clock usually by integer division. Fractional-N frequency dividers (FFDs) are needed when the clock required by a block in MCD system is not possible to be derived by simple integer division. In this paper, we present such a FFD with an improved resolution of (1/8). Post layout simulation results after parasitic RC extraction in the 90-nm technology node show that our FFD is able to fractionally divide signals upto 2 GHz frequency with an average error of 0.11% in division ratio even with 2.5° phase error at the input. Our FFD consumes 754 μW when fractionally dividing a 2 GHz signal with a resolution of (1/8).

In this work, a novel and efficient approach is proposed to optimize linearity and efficiency of a power amplifier used in mobile communication applications. A linear and high performance push amplifier is designed and analyzed to extract design equations for an optimum performance. The proposed push amplifier has two sections; an analog section and a switching section. The analog section provides the required linearity and the switching section guarantees the satisfaction of the total efficiency level. Double power supply scheme is used in push amplifiers to enhance its performance. Two separate power supplies are employed for linear and switching sections of push amplifiers which have different voltage levels. The implemented circuit is simulated using HSPICERF with TSMC models for active and passive elements. The proposed power amplifier (PA) provides a maximum output power of 25 dBm and power added efficiency (PAE) as high as 51% at 2.5 GHz operation frequency. At 1-dB compression point, this PA exhibits output power of 25 dBm with 48% PAE and 4.5% error vector magnitude (EVM) which is appropriate for 64QAM OFDM signals.

This paper describes the design and operation of a high output impedance tissue current driver circuit, for use in medical electronics, such as electrical impedance tomography (EIT). This novel architecture was designed for implementation in bipolar technology, to meet the specifications for EIT, namely operating frequency range 10 kHz–1 MHz with a target output resistance of 16 MΩ. Simulation results are presented, showing that the current source more than met the minimum specification for EIT.

This paper presents, a novel digital foreground calibration technique in order to reduce the effects of timing-skew in time-interleaved analog-to-digital converters (ADCs). The proposed technique implementation is simple and helps to achieve very low power consumption. This technique is based on the using of a simple reference comparator which is synchronized by one of sub-channels in each cycle of calibration. Also the detection and correction are implemented by a simple LMS loop that guarantee the convergence of algorithm. Finally, simulation results show that the new approach method can effectively correct timing errors for a specified input signal, and achieves a low power consumption, low computational complexity and high convergence speed and also verify theoretical equations for it.

The memristor has drawn the worldwide attention since it has been discovered at HP laboratory on 1 May 2008. Since then many researchers are taking efforts to find its applications in various areas. In this paper, we study the filter characteristics of first-order low pass and high pass filters employing memristor with a capacitor. The paper provides a comparative analysis between low pass and high pass filter circuits that utilizing ordinary resistor or memristor with a capacitor. The theoretical analyzes are verified with SPICE simulation results using a memristor SPICE model with nonlinear dopant drift and MATLAB environment. The effect of change of the input frequency and initial resistance value of memristor on the cut-off frequencies of the presented low pass and high pass filters are investigated. The memory effect of memristor is represented by simulation results.

This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). The timing error is detected by using the first derivative of the channel ADCs and a least-mean-square (LMS) loop is exploited to compensate the timing skew. The proposed scheme is effective within the entire frequency range of 0–f_s/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes lesser power and smaller area.

In the field of robotics, one of the essential tasks for a robot to accomplish its goals is to know its own location. The localization problem is a complex task and, usually, different systems, methods and sensors are needed to achieve it. One of these methods is the iterative closest points (ICP) algorithm. The main problem that ICP presents is its high computational time. Due to this, it is common to filter its input data before calculating the final transformation. In this paper, a comparative study in terms of precision and execution time among the most popular filters used in combination with the ICP is presented. The study indicates that the scale-invariant feature transform (SIFT) is the filter that better improves the execution time, while its combination with the RANdom SAmple Consensus (RANSAC) obtains better precision results.

This study presents a unified hybrid architecture to compute the inverse discrete cosine transform (IDCT) of multiple modern video decoders such as moving picture experts group (MPEG-4), H.264, VC-1 and high efficiency video coding (HEVC). The proposed hardware sharing architecture requires a lower hardware cost than that for individual implementations, and maximizes the proportion of the circuit that is reused during the computation. The proposed architecture design needs only adders and shifters to significantly reduce the hardware cost. Thus, the resource sharing method can increase the circuit sharing capability and achieve high hardware efficiency. For verification, a TSMC 0.18-μm CMOS process is applied to implement the IDCT chip, and the maximum throughput rate of the proposed design is 1000 MP/s with a hardware cost of 16.5 k gates.