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DIGITAL BACKGROUND CALIBRATION FOR TIMING SKEW IN TIME-INTERLEAVED ADC

State Key Lab of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Room 1003, Building 211, No. 4, Section 2, North Jianshe Road, Chengdu 610054, P. R. China

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YANG LIU

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SHUANGYI WU

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NING NING

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, and

QI YU

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https://doi.org/10.1142/S0218126614501175Cited by:1 (Source: Crossref)

Abstract

This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). The timing error is detected by using the first derivative of the channel ADCs and a least-mean-square (LMS) loop is exploited to compensate the timing skew. The proposed scheme is effective within the entire frequency range of 0–f_s/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes lesser power and smaller area.

This paper was recommended by Regional Editor Piero Malcovati.

Keywords:

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