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This paper presents, a novel digital foreground calibration technique in order to reduce the effects of timing-skew in time-interleaved analog-to-digital converters (ADCs). The proposed technique implementation is simple and helps to achieve very low power consumption. This technique is based on the using of a simple reference comparator which is synchronized by one of sub-channels in each cycle of calibration. Also the detection and correction are implemented by a simple LMS loop that guarantee the convergence of algorithm. Finally, simulation results show that the new approach method can effectively correct timing errors for a specified input signal, and achieves a low power consumption, low computational complexity and high convergence speed and also verify theoretical equations for it.

This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). The timing error is detected by using the first derivative of the channel ADCs and a least-mean-square (LMS) loop is exploited to compensate the timing skew. The proposed scheme is effective within the entire frequency range of 0–f_s/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes lesser power and smaller area.

This paper presents an 8-bit configurable time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). By using a mode selection circuit, four modes of sampling rate are provided: Single channel at 333.3 MS/s, 2-channel at 666.7 MS/s, 3-channel at 1 GS/s and 6-channel at 2 GS/s. An on-chip delay-locked loop (DLL) uniformly generates six-phase clock with 20% duty cycle, and the timing errors are reduced to a tolerable range. In low sampling rate modes, the corresponding sampling switches and comparators in the idle sub-ADCs are shut down to save power consumption. Based on the 65-nm CMOS technology, the post-layout simulation results show that at 1.2 V supply, the proposed ADC consumes 8.6, 10.9, 13.1 and 19.9 mW under different modes. With an ENOB of 7.92, 7.34, 7.01 and 6.37 bit, this results in a FOM of 106.6, 100.9, 101.6 and 120.3 fJ/conversion-step respectively.

This paper presents a 10-GS/s 6-bit track-and-hold amplifier (THA), which is designed for a 16-way time-interleaved successive approximation register (SAR) analog to digital converter (ADC). To extend the bandwidth, a differential source-degenerated common-source amplifier with peaking inductance is adopted as an input buffer. A switched source follower master track-and-hold stage samples the 800-mV_PP differential input signal at 10GHz. Moreover, the THA cancels the feed-through in hold mode by a clock-controlled transistor. The proposed THA is simulated in 65-nm CMOS technology. It operates with 1.8/1.2-V supply and consumes 84.8mW. At a sampling rate of 10GS/s, $-$41-dB total harmonic distortion (THD) is achieved with input frequencies up to 5GHz.

In time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches, caused by the limited bandwidth of input signal traces and sample circuits, seriously deteriorate the spurious-free dynamic range (SFDR) of the system. This paper analyzes the influence of bandwidth mismatch errors under different sampling sequences. Eventually, based on a randomization technique and the simulated annealing algorithm (SAA), a bandwidth mismatch optimization technique is presented that can work well with other bandwidth mismatch calibration methods. The behavior simulation results indicate that an improvement of 7dB in the SFDR can be achieved with this technique in a 16-channel TI-ADC after timing and gain calibration.

This paper proposes a full-band calibration scheme of timing mismatch for Time-Interleaved Analog-to-Digital Converters (TI-ADC) based on Automatic Identification (AI) detection scheme. Besides estimating the value of timing mismatch, AI detection scheme also judges the odd–even property of the Nyquist zone (NZ) which the input signal belongs to and thus adaptively adjusts the calibration polarity for full-band application. On the other hand, Successive-Approximation-Register (SAR) correction technique is employed to speed up the convergence process of calibration with low cost. The efficiency of the proposed calibration scheme is verified by MATLAB simulation and implementation on PCB. Both results show that with an input signal whose bandwidth is within any NZ, the proposed calibration methodology is effective. Compared with the traditional calibration schemes, the proposed calibration method achieves fast convergence speed with $6\times 10^3$ samples and costs less hardware with 2.1k gate counts.

Time-interleaving has been a popular choice for multi-GHz analog-to-digital converters (ADCs) with a resolution of 8–14 bits. Unfortunately, inherent defects such as offset, gain, timing-skew mismatches among sub-ADCs degrade overall performance seriously. At present, the method for eliminating offset and gain mismatch is fairly straightforward; however, calibration for timing-skew is still in a state of exploration. A systematic overview of various calibration methods for timing-skew in time-interleaved ADCs (TI-ADCs) has been provided in this paper. Meanwhile, current state-of-the-art TI-ADCs recently are reported and several noteworthy trends can be observed from the statistical results.

This paper presents a 6.4-GS/s 16-way 10-bit time-interleaved (TI) SAR ADC for wideband wireless applications. A two-stage master–slave hierarchical sampling network, which is immune to the time skew of multi-phase clocks, is introduced to avoid the time-skew calibration for design simplicity and hardware efficiency. To perform low distortion and fast sampling at acceptable power consumption, a linearity- and energy efficiency-improved track-and-hold (T&H) buffer with current-feedback compensation scheme is proposed. Accompanied by its low-output-impedance feature, the buffer obtains adequate bandwidth which can cover the entire ADC Nyquist sampling range. Moreover, the split capacitor DAC combined with a novel nonbinary algorithm is adopted in single-channel ADC, enabling a shorter DAC settling time as well as less switching energy. Capacitor mismatch effect with related design trade-off is discussed and behavior models are built to evaluate the effect of capacitor mismatch on ENOB. An asynchronous self-triggered SAR logic is designed and optimized to minimize the delay on logic paths to match up the acceleration on DAC and comparator. With these proposed techniques, the 10-b sub-ADC achieves a 400-MHz conversion rate with only 3.5-mW power consumption. The circuit is designed and simulated in TSMC 28 HPC process and the results show that the overall ADC achieves 54.6-dB SNDR and 58.1-dB SFDR at Nyquist input while consuming 127-mW power from 1-V/1.5-V supply and achieving a Walden FoM of 45fJ/conv-step.

This paper presents a 32-GS/s front-end sampling circuit (FESC) in 65-nm CMOS. The FESC is designed for a 32-channel time-interleaved analog-to-digital converter (ADC), and the $4\times 8$ two-stage interleaving structure leads to a good trade-off between bandwidth and linearity. The analysis and cancellation of charge injection, clock feedthrough, and signal feedthrough are presented. Inductor peaking technique is adopted to extend the bandwidth of the buffer between the first and the second stage. Based on the simulation results, the proposed FESC consumes 136mW at 32 GS/s, and the signal-to-noise ratio (SNDR) is up to 39.55 dB at Nyquist input, achieving a state-of-the-art power efficiency.

This paper presents a new design for the optimization of analog to digital sigma delta-coupling noise annotations. The proposed technique increases the level of the signal-to quantization-noise-ratio (SQNR) by improving the zero of the noise transfer function, which leads to an increase in signal to noise. In the new SQNR design, the modulator rises up to 8.5 db. The proposed structure of the first-order dual-channel sigma-delta modulator is also presented.