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A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS

Shaanxi Key Lab. of Integrated Circuits and Systems, School of Microelectronics Xidian University, Xi’an 710071, P. R. China

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Dengquan Li

Shaanxi Key Lab. of Integrated Circuits and Systems, School of Microelectronics Xidian University, Xi’an 710071, P. R. China

E-mail Address: dqli@xidian.edu.cn

Corresponding author.

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Henghui Mao

Shaanxi Key Lab. of Integrated Circuits and Systems, School of Microelectronics Xidian University, Xi’an 710071, P. R. China

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Ruixue Ding

Shaanxi Key Lab. of Integrated Circuits and Systems, School of Microelectronics Xidian University, Xi’an 710071, P. R. China

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, and

Zhangming Zhu

Shaanxi Key Lab. of Integrated Circuits and Systems, School of Microelectronics Xidian University, Xi’an 710071, P. R. China

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https://doi.org/10.1142/S0218126621501437Cited by:2 (Source: Crossref)

Abstract

This paper presents a 32-GS/s front-end sampling circuit (FESC) in 65-nm CMOS. The FESC is designed for a 32-channel time-interleaved analog-to-digital converter (ADC), and the $4 \times 8$ $4 \times 8$ two-stage interleaving structure leads to a good trade-off between bandwidth and linearity. The analysis and cancellation of charge injection, clock feedthrough, and signal feedthrough are presented. Inductor peaking technique is adopted to extend the bandwidth of the buffer between the first and the second stage. Based on the simulation results, the proposed FESC consumes 136mW at 32 GS/s, and the signal-to-noise ratio (SNDR) is up to 39.55 dB at Nyquist input, achieving a state-of-the-art power efficiency.

This paper was recommended by Regional Editor Piero Malcovati.

Keywords:

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